riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Rename PRCI to CoreplexLocalInterrupter

Browse Source 
That's all it's doing (there wasn't much PRC).
This commit is contained in:
Andrew Waterman
2016-09-16 14:26:34 -07:00
parent 4b1de82c1d
commit 86b70c8c59
5 changed files with 50 additions and 55 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/coreplex/Coreplex.scala
View File

@ -56,7 +56,7 @@ abstract class Coreplex(implicit val p: Parameters, implicit val c: CoreplexConf
val slave = Vec(c.nSlaves, new ClientUncachedTileLinkIO()(innerParams)).flip
val interrupts = Vec(c.nExtInterrupts, Bool()).asInput
val debug = new DebugBusIO()(p).flip
val prci = Vec(c.nTiles, new PRCITileIO).flip
val clint = Vec(c.nTiles, new CoreplexLocalInterrupts).asInput
val success: Option[Bool] = hasSuccessFlag.option(Bool(OUTPUT))
}
@ -147,8 +147,8 @@ class DefaultCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp,
// connect coreplex-internal interrupts to tiles
for (((tile, tileReset), i) <- (tileList zip tileResets) zipWithIndex) {
tileReset := io.prci(i).reset
tile.io.interrupts := io.prci(i).interrupts
tileReset := reset // TODO should tiles be reset separately from coreplex?
tile.io.interrupts := io.clint(i)
tile.io.interrupts.meip := plic.io.harts(plic.cfg.context(i, 'M'))
tile.io.interrupts.seip.foreach(_ := plic.io.harts(plic.cfg.context(i, 'S')))
tile.io.interrupts.debug := debugModule.io.debugInterrupts(i)