riscv/rocket-chip
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For vlsi, make Memdessert elaborate before Top so the generated Makefrag-tests doesn't get overwritten

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This commit is contained in:
Henry Cook 2015-07-23 17:00:22 -07:00
parent caf89baeb7
commit 866396545d
1 changed files with 1 additions and 1 deletions
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Makefrag
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@ -25,7 +25,7 @@ timeout_cycles = 100000000
# Verilog Generation # Verilog Generation
#-------------------------------------------------------------------- #--------------------------------------------------------------------
$(generated_dir)/$(MODEL).$(CONFIG).v: $(chisel_srcs) $(generated_dir)/$(MODEL).$(CONFIG).v: $(chisel_srcs) $(generated_dir)/memdessertMemDessert.$(CONFIG).v
cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "run $(MODEL) --backend $(BACKEND) --targetDir $(generated_dir) --W0W --configDump --noInlineMem --configInstance rocketchip.$(CONFIG)" cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "run $(MODEL) --backend $(BACKEND) --targetDir $(generated_dir) --W0W --configDump --noInlineMem --configInstance rocketchip.$(CONFIG)"
cd $(generated_dir) && \ cd $(generated_dir) && \
if [ -a $(MODEL).$(CONFIG).conf ]; then \ if [ -a $(MODEL).$(CONFIG).conf ]; then \