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syncregs: Not sure the use case for SynchronizerShiftRegInit, so remove it YAGNI

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This commit is contained in:
Megan Wachs 2017-08-24 17:47:04 -07:00
parent 4e773f4738
commit 85c39b2f97
1 changed files with 0 additions and 27 deletions
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27
src/main/scala/util/SynchronizingReg.scala
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@ -13,7 +13,6 @@ import Chisel._
* *
* The 3 different types vary in their reset behavior: * The 3 different types vary in their reset behavior:
* AsyncResetSynchronizerShiftReg -- asynchronously reset to 0 * AsyncResetSynchronizerShiftReg -- asynchronously reset to 0
* SynchronizerShiftRegInit -- synchronously reset to 0
* SynchronizerShiftReg -- no reset, pipeline only. * SynchronizerShiftReg -- no reset, pipeline only.
* *
*/ */
@ -64,32 +63,6 @@ object AsyncResetSynchronizerShiftReg {
in, sync, name) in, sync, name)
} }
class SynchronizerShiftRegInit(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg {
override def desiredName = s"SynchronizerShiftRegInit_w${w}_d${sync}"
val syncv = List.tabulate(sync) { i =>
val r = RegInit(UInt(0, width = w))
r.suggestName(s"sync_${i}")
}
syncv.last := io.d
(syncv.init zip syncv.tail).foreach { case (sink, source) =>
sink := source
}
io.q := syncv.head
}
object SynchronizerShiftRegInit {
def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T =
AbstractSynchronizerReg(gen = (w: Int, sync: Int) => { new SynchronizerShiftRegInit(w, sync)},
in, sync, name)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg { class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg {
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"