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devices: add reg-names to most devices

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This commit is contained in:
Wesley W. Terpstra 2017-06-28 13:01:40 -07:00
parent 0bf46edb6c
commit 84dc23c215
9 changed files with 10 additions and 13 deletions
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2
src/main/scala/rocket/ICache.scala
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@ -46,7 +46,7 @@ class ICache(val icacheParams: ICacheParams, val hartid: Int)(implicit p: Parame
TLManagerNode(Seq(TLManagerPortParameters(
Seq(TLManagerParameters(
address = Seq(AddressSet(itimAddr, size-1)),
resources = device.reg,
resources = device.reg("mem"),
regionType = RegionType.UNCACHED,
executable = true,
supportsPutFull = TransferSizes(1, wordBytes),

2
src/main/scala/rocket/ScratchpadSlavePort.scala
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@ -19,7 +19,7 @@ class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends L
val node = TLManagerNode(Seq(TLManagerPortParameters(
Seq(TLManagerParameters(
address = List(address),
resources = device.reg,
resources = device.reg("mem"),
regionType = RegionType.UNCACHED,
executable = true,
supportsArithmetic = if (usingAtomics) TransferSizes(4, coreDataBytes) else TransferSizes.none,

2
src/main/scala/uncore/devices/Rom.scala
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@ -13,7 +13,7 @@ import uncore.util._
import config._
class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4,
resources: Seq[Resource] = new SimpleDevice("rom", Nil).reg)(implicit p: Parameters) extends LazyModule
resources: Seq[Resource] = new SimpleDevice("rom", Nil).reg("mem"))(implicit p: Parameters) extends LazyModule
{
val node = TLManagerNode(beatBytes, TLManagerParameters (

3
src/main/scala/uncore/devices/debug/Debug.scala
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@ -283,7 +283,6 @@ class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyMod
val dmiNode = TLRegisterNode (
address = AddressSet.misaligned(DMI_DMCONTROL << 2, 4),
device = device,
deviceKey = "reg",
beatBytes = 4,
executable = false
)
@ -430,7 +429,6 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
address = AddressSet.misaligned(0, DMI_RegAddrs.DMI_DMCONTROL << 2) ++
AddressSet.misaligned((DMI_RegAddrs.DMI_DMCONTROL + 1) << 2, (0x200 - ((DMI_RegAddrs.DMI_DMCONTROL + 1) << 2))),
device = device,
deviceKey = "reg",
beatBytes = 4,
executable = false
)
@ -438,7 +436,6 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
val tlNode = TLRegisterNode(
address=Seq(AddressSet(0, 0xFFF)), // This is required for correct functionality, it's not configurable.
device=device,
deviceKey="reg",
beatBytes=p(XLen)/8,
executable=true
)

2
src/main/scala/uncore/tilelink2/Error.scala
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@ -14,7 +14,7 @@ class TLError(address: Seq[AddressSet], beatBytes: Int = 4)(implicit p: Paramete
val node = TLManagerNode(Seq(TLManagerPortParameters(
Seq(TLManagerParameters(
address = address,
resources = device.reg,
resources = device.reg("mem"),
supportsGet = TransferSizes(1, beatBytes),
supportsPutPartial = TransferSizes(1, beatBytes),
supportsPutFull = TransferSizes(1, beatBytes),

6
src/main/scala/uncore/tilelink2/RegisterRouter.scala
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@ -11,7 +11,7 @@ import scala.math.{min,max}
class TLRegisterNode(
address: Seq[AddressSet],
device: Device,
deviceKey: String = "reg",
deviceKey: String = "reg/control",
concurrency: Int = 0,
beatBytes: Int = 4,
undefZero: Boolean = true,
@ -88,7 +88,7 @@ object TLRegisterNode
def apply(
address: Seq[AddressSet],
device: Device,
deviceKey: String = "reg",
deviceKey: String = "reg/control",
concurrency: Int = 0,
beatBytes: Int = 4,
undefZero: Boolean = true,
@ -103,7 +103,7 @@ object TLRegisterNode
abstract class TLRegisterRouterBase(devname: String, devcompat: Seq[String], val address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean)(implicit p: Parameters) extends LazyModule
{
val device = new SimpleDevice(devname, devcompat)
val node = TLRegisterNode(Seq(address), device, "reg", concurrency, beatBytes, undefZero, executable)
val node = TLRegisterNode(Seq(address), device, "reg/control", concurrency, beatBytes, undefZero, executable)
val intnode = IntSourceNode(IntSourcePortSimple(num = interrupts, resources = Seq(Resource(device, "int"))))
}

2
src/main/scala/uncore/tilelink2/SRAM.scala
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@ -14,7 +14,7 @@ class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4,
val node = TLManagerNode(Seq(TLManagerPortParameters(
Seq(TLManagerParameters(
address = List(address),
resources = device.reg,
resources = device.reg("mem"),
regionType = RegionType.UNCACHED,
executable = executable,
supportsGet = TransferSizes(1, beatBytes),

2
src/main/scala/uncore/tilelink2/TestRAM.scala
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@ -15,7 +15,7 @@ class TLTestRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int
val node = TLManagerNode(Seq(TLManagerPortParameters(
Seq(TLManagerParameters(
address = List(address),
resources = device.reg,
resources = device.reg("mem"),
regionType = RegionType.UNCACHED,
executable = executable,
supportsGet = TransferSizes(1, beatBytes),

2
src/main/scala/uncore/tilelink2/Zero.scala
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@ -13,7 +13,7 @@ class TLZero(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4
val node = TLManagerNode(Seq(TLManagerPortParameters(
Seq(TLManagerParameters(
address = List(address),
resources = device.reg,
resources = device.reg("mem"),
regionType = RegionType.UNCACHED,
executable = executable,
supportsGet = TransferSizes(1, beatBytes),