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devices: add reg-names to most devices

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This commit is contained in:
Wesley W. Terpstra
2017-06-28 13:01:40 -07:00
parent 0bf46edb6c
commit 84dc23c215
9 changed files with 10 additions and 13 deletions
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2
src/main/scala/uncore/devices/Rom.scala
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@ -13,7 +13,7 @@ import uncore.util._
import config._
class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4,
resources: Seq[Resource] = new SimpleDevice("rom", Nil).reg)(implicit p: Parameters) extends LazyModule
resources: Seq[Resource] = new SimpleDevice("rom", Nil).reg("mem"))(implicit p: Parameters) extends LazyModule
{
val node = TLManagerNode(beatBytes, TLManagerParameters (

3
src/main/scala/uncore/devices/debug/Debug.scala
View File

@ -283,7 +283,6 @@ class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyMod
val dmiNode = TLRegisterNode (
address = AddressSet.misaligned(DMI_DMCONTROL << 2, 4),
device = device,
deviceKey = "reg",
beatBytes = 4,
executable = false
)
@ -430,7 +429,6 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
address = AddressSet.misaligned(0, DMI_RegAddrs.DMI_DMCONTROL << 2) ++
AddressSet.misaligned((DMI_RegAddrs.DMI_DMCONTROL + 1) << 2, (0x200 - ((DMI_RegAddrs.DMI_DMCONTROL + 1) << 2))),
device = device,
deviceKey = "reg",
beatBytes = 4,
executable = false
)
@ -438,7 +436,6 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
val tlNode = TLRegisterNode(
address=Seq(AddressSet(0, 0xFFF)), // This is required for correct functionality, it's not configurable.
device=device,
deviceKey="reg",
beatBytes=p(XLen)/8,
executable=true
)