riscv/rocket-chip
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devices: add reg-names to most devices

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This commit is contained in:
Wesley W. Terpstra
2017-06-28 13:01:40 -07:00
parent 0bf46edb6c
commit 84dc23c215
9 changed files with 10 additions and 13 deletions
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2
src/main/scala/rocket/ICache.scala
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@ -46,7 +46,7 @@ class ICache(val icacheParams: ICacheParams, val hartid: Int)(implicit p: Parame
TLManagerNode(Seq(TLManagerPortParameters(
Seq(TLManagerParameters(
address = Seq(AddressSet(itimAddr, size-1)),
resources = device.reg,
resources = device.reg("mem"),
regionType = RegionType.UNCACHED,
executable = true,
supportsPutFull = TransferSizes(1, wordBytes),

2
src/main/scala/rocket/ScratchpadSlavePort.scala
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@ -19,7 +19,7 @@ class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends L
val node = TLManagerNode(Seq(TLManagerPortParameters(
Seq(TLManagerParameters(
address = List(address),
resources = device.reg,
resources = device.reg("mem"),
regionType = RegionType.UNCACHED,
executable = true,
supportsArithmetic = if (usingAtomics) TransferSizes(4, coreDataBytes) else TransferSizes.none,