From 847efde385ed10cc3fdae8514fb5fc362abe5e82 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Fri, 5 Jan 2018 12:47:41 -0800 Subject: [PATCH] coreplex: dontTouch the tile_inputs wire --- src/main/scala/coreplex/HasTiles.scala | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/main/scala/coreplex/HasTiles.scala b/src/main/scala/coreplex/HasTiles.scala index 82436651..49a958f8 100644 --- a/src/main/scala/coreplex/HasTiles.scala +++ b/src/main/scala/coreplex/HasTiles.scala @@ -3,6 +3,7 @@ package freechips.rocketchip.coreplex import Chisel._ +import chisel3.experimental.dontTouch import freechips.rocketchip.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.interrupts._ @@ -37,9 +38,9 @@ trait HasTilesModuleImp extends LazyModuleImp vectors.head.getWidth } - val tile_inputs = Wire(Vec(outer.nTiles, new ClockedTileInputs()(p.alterPartial { + val tile_inputs = dontTouch(Wire(Vec(outer.nTiles, new ClockedTileInputs()(p.alterPartial { case SharedMemoryTLEdge => outer.sharedMemoryTLEdge - }))) + })))) // dontTouch keeps constant prop from sucking these signals into the tile // Unconditionally wire up the non-diplomatic tile inputs outer.tiles.map(_.module).zip(tile_inputs).foreach { case(tile, wire) =>