Removed all traces of params

rocket/src/main/scala/tile.scala

@@ -11,22 +11,27 @@ case object NDCachePorts extends Field[Int]
 case object NPTWPorts extends Field[Int]
 case object BuildRoCC extends Field[Option[() => RoCC]]
 
-abstract class Tile(resetSignal: Bool = null) extends Module(_reset = resetSignal) {
+abstract class Tile(resetSignal: Bool = null)
+                   (implicit p: Parameters) extends Module(_reset = resetSignal) {
   val io = new Bundle {
     val cached = new ClientTileLinkIO
     val uncached = new ClientUncachedTileLinkIO
-    val host = new HTIFIO
+    val host = new HtifIO
   }
 }
 
-class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) {
-  val icache = Module(new Frontend, { case CacheName => "L1I"; case CoreName => "Rocket" })
-  val dcache = Module(new HellaCache, { case CacheName => "L1D" })
-  val ptw = Module(new PTW(params(NPTWPorts)))
-  val core = Module(new Rocket, { case CoreName => "Rocket" })
+class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(resetSignal)(p) {
+  //TODO
+  val dcacheParams = p.alterPartial({ case CacheName => "L1D" })
+  val icache = Module(new Frontend()(p.alterPartial({
+                 case CacheName => "L1I"
+                 case CoreName => "Rocket" })))
+  val dcache = Module(new HellaCache()(dcacheParams))
+  val ptw = Module(new PTW(p(NPTWPorts))(dcacheParams))
+  val core = Module(new Rocket()(p.alterPartial({ case CoreName => "Rocket" })))
 
   dcache.io.cpu.invalidate_lr := core.io.dmem.invalidate_lr // Bypass signal to dcache
-  val dcArb = Module(new HellaCacheArbiter(params(NDCachePorts)))
+  val dcArb = Module(new HellaCacheArbiter(p(NDCachePorts))(dcacheParams))
   dcArb.io.requestor(0) <> ptw.io.mem
   dcArb.io.requestor(1) <> core.io.dmem
   dcache.io.cpu <> dcArb.io.mem
@@ -39,20 +44,16 @@ class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) {
   core.io.ptw <> ptw.io.dpath
 
   //If so specified, build an FPU module and wire it in
-  params(BuildFPU)
-    .map { bf => bf() }
-    .foreach { fpu =>
-      core.io.fpu <> fpu.io
-    }
+  p(BuildFPU) foreach { fpu => core.io.fpu <> fpu(p).io }
 
   // Connect the caches and ROCC to the outer memory system
   io.cached <> dcache.io.mem
   // If so specified, build an RoCC module and wire it in
   // otherwise, just hookup the icache
-  io.uncached <> params(BuildRoCC).map { buildItHere =>
+  io.uncached <> p(BuildRoCC).map { buildItHere =>
     val rocc = buildItHere()
     val memArb = Module(new ClientTileLinkIOArbiter(3))
-    val dcIF = Module(new SimpleHellaCacheIF)
+    val dcIF = Module(new SimpleHellaCacheIF()(dcacheParams))
     core.io.rocc <> rocc.io
     dcIF.io.requestor <> rocc.io.mem
     dcArb.io.requestor(2) <> dcIF.io.cache