Removed all traces of params
This commit is contained in:
Henry Cook
@ -7,10 +7,9 @@ import junctions._
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import uncore._
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import Util._
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case object BuildFPU extends Field[Option[() => FPU]]
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case object BuildFPU extends Field[Option[Parameters => FPU]]
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case object FDivSqrt extends Field[Boolean]
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case object XLen extends Field[Int]
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case object NMultXpr extends Field[Int]
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case object FetchWidth extends Field[Int]
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case object RetireWidth extends Field[Int]
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case object UseVM extends Field[Boolean]
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@ -23,59 +22,65 @@ case object CoreDataBits extends Field[Int]
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case object CoreDCacheReqTagBits extends Field[Int]
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case object NCustomMRWCSRs extends Field[Int]
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abstract trait CoreParameters extends UsesParameters {
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val xLen = params(XLen)
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val paddrBits = params(PAddrBits)
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val vaddrBits = params(VAddrBits)
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val pgIdxBits = params(PgIdxBits)
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val ppnBits = params(PPNBits)
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val vpnBits = params(VPNBits)
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val pgLevels = params(PgLevels)
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val pgLevelBits = params(PgLevelBits)
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val asIdBits = params(ASIdBits)
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trait HasCoreParameters {
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implicit val p: Parameters
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val xLen = p(XLen)
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val paddrBits = p(PAddrBits)
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val vaddrBits = p(VAddrBits)
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val pgIdxBits = p(PgIdxBits)
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val ppnBits = p(PPNBits)
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val vpnBits = p(VPNBits)
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val pgLevels = p(PgLevels)
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val pgLevelBits = p(PgLevelBits)
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val asIdBits = p(ASIdBits)
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val retireWidth = params(RetireWidth)
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val coreFetchWidth = params(FetchWidth)
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val coreInstBits = params(CoreInstBits)
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val retireWidth = p(RetireWidth)
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val fetchWidth = p(FetchWidth)
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val coreInstBits = p(CoreInstBits)
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val coreInstBytes = coreInstBits/8
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val coreDataBits = xLen
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val coreDataBytes = coreDataBits/8
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val coreDCacheReqTagBits = params(CoreDCacheReqTagBits)
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val coreDCacheReqTagBits = p(CoreDCacheReqTagBits)
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val coreMaxAddrBits = math.max(ppnBits,vpnBits+1) + pgIdxBits
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val vaddrBitsExtended = vaddrBits + (vaddrBits < xLen).toInt
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val mmioBase = params(MMIOBase)
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val mmioBase = p(MMIOBase)
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val nCustomMrwCsrs = p(NCustomMRWCSRs)
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val usingVM = p(UseVM)
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val usingFPU = !p(BuildFPU).isEmpty
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val usingFDivSqrt = p(FDivSqrt)
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val usingRoCC = !p(BuildRoCC).isEmpty
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val usingFastMulDiv = p(FastMulDiv)
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val fastLoadWord = p(FastLoadWord)
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val fastLoadByte = p(FastLoadByte)
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// Print out log of committed instructions and their writeback values.
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// Requires post-processing due to out-of-order writebacks.
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val EnableCommitLog = false
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val enableCommitLog = false
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val usingPerfCounters = p(UsePerfCounters)
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if(params(FastLoadByte)) require(params(FastLoadWord))
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if (fastLoadByte) require(fastLoadWord)
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}
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abstract trait RocketCoreParameters extends CoreParameters
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{
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require(params(FetchWidth) == 1) // for now...
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require(params(RetireWidth) == 1) // for now...
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}
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abstract class CoreModule(implicit val p: Parameters) extends Module
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with HasCoreParameters
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abstract class CoreBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasCoreParameters
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abstract class CoreBundle extends Bundle with CoreParameters
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abstract class CoreModule extends Module with CoreParameters
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class Rocket extends CoreModule
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{
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class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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val io = new Bundle {
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val host = new HTIFIO
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val imem = new CPUFrontendIO
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val dmem = new HellaCacheIO
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val host = new HtifIO
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val imem = new FrontendIO()(p.alterPartial({case CacheName => "L1I" }))
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val dmem = new HellaCacheIO()(p.alterPartial({ case CacheName => "L1D" }))
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val ptw = new DatapathPTWIO().flip
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val fpu = new FPUIO().flip
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val rocc = new RoCCInterface().flip
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}
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var decode_table = XDecode.table
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if (!params(BuildFPU).isEmpty) decode_table ++= FDecode.table
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if (!params(BuildFPU).isEmpty && params(FDivSqrt)) decode_table ++= FDivSqrtDecode.table
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if (!params(BuildRoCC).isEmpty) decode_table ++= RoCCDecode.table
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if (usingFPU) decode_table ++= FDecode.table
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if (usingFPU && usingFDivSqrt) decode_table ++= FDivSqrtDecode.table
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if (usingRoCC) decode_table ++= RoCCDecode.table
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val ex_ctrl = Reg(new IntCtrlSigs)
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val mem_ctrl = Reg(new IntCtrlSigs)
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@ -123,7 +128,7 @@ class Rocket extends CoreModule
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// decode stage
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val id_pc = io.imem.resp.bits.pc
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val id_inst = io.imem.resp.bits.data(0).toBits; require(params(FetchWidth) == 1)
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val id_inst = io.imem.resp.bits.data(0).toBits; require(fetchWidth == 1)
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val id_ctrl = Wire(new IntCtrlSigs()).decode(id_inst, decode_table)
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val id_raddr3 = id_inst(31,27)
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val id_raddr2 = id_inst(24,20)
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@ -156,7 +161,7 @@ class Rocket extends CoreModule
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val id_amo_rl = id_inst(25)
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val id_fence_next = id_ctrl.fence || id_ctrl.amo && id_amo_rl
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val id_mem_busy = !io.dmem.ordered || io.dmem.req.valid
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val id_rocc_busy = Bool(!params(BuildRoCC).isEmpty) &&
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val id_rocc_busy = Bool(usingRoCC) &&
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(io.rocc.busy || ex_reg_valid && ex_ctrl.rocc ||
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mem_reg_valid && mem_ctrl.rocc || wb_reg_valid && wb_ctrl.rocc)
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id_reg_fence := id_fence_next || id_reg_fence && id_mem_busy
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@ -169,8 +174,8 @@ class Rocket extends CoreModule
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(id_illegal_insn, UInt(Causes.illegal_instruction))))
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val dcache_bypass_data =
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if(params(FastLoadByte)) io.dmem.resp.bits.data
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else if(params(FastLoadWord)) io.dmem.resp.bits.data_word_bypass
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if (fastLoadByte) io.dmem.resp.bits.data
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else if (fastLoadWord) io.dmem.resp.bits.data_word_bypass
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else wb_reg_wdata
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// detect bypass opportunities
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@ -207,8 +212,9 @@ class Rocket extends CoreModule
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alu.io.in1 := ex_op1.toUInt
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// multiplier and divider
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val div = Module(new MulDiv(mulUnroll = if(params(FastMulDiv)) 8 else 1,
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earlyOut = params(FastMulDiv)))
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val div = Module(new MulDiv(width = xLen,
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unroll = if(usingFastMulDiv) 8 else 1,
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earlyOut = usingFastMulDiv))
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div.io.req.valid := ex_reg_valid && ex_ctrl.div
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div.io.req.bits.dw := ex_ctrl.alu_dw
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div.io.req.bits.fn := ex_ctrl.alu_fn
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@ -345,7 +351,7 @@ class Rocket extends CoreModule
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val ll_wdata = Wire(init = div.io.resp.bits.data)
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val ll_waddr = Wire(init = div.io.resp.bits.tag)
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val ll_wen = Wire(init = div.io.resp.fire())
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if (!params(BuildRoCC).isEmpty) {
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if (usingRoCC) {
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io.rocc.resp.ready := !(wb_reg_valid && wb_ctrl.wxd)
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when (io.rocc.resp.fire()) {
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div.io.resp.ready := Bool(false)
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@ -356,7 +362,7 @@ class Rocket extends CoreModule
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}
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when (dmem_resp_replay && dmem_resp_xpu) {
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div.io.resp.ready := Bool(false)
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if (!params(BuildRoCC).isEmpty)
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if (usingRoCC)
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io.rocc.resp.ready := Bool(false)
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ll_waddr := dmem_resp_waddr
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ll_wen := Bool(true)
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@ -410,7 +416,7 @@ class Rocket extends CoreModule
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// stall for RAW/WAW hazards on CSRs, LB/LH, and mul/div in memory stage.
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val mem_mem_cmd_bh =
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if (params(FastLoadWord)) Bool(!params(FastLoadByte)) && mem_reg_slow_bypass
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if (fastLoadWord) Bool(!fastLoadByte) && mem_reg_slow_bypass
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else Bool(true)
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val mem_cannot_bypass = mem_ctrl.csr != CSR.N || mem_ctrl.mem && mem_mem_cmd_bh || mem_ctrl.div || mem_ctrl.fp || mem_ctrl.rocc
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val data_hazard_mem = mem_ctrl.wxd && checkHazards(hazard_targets, _ === mem_waddr)
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@ -423,7 +429,7 @@ class Rocket extends CoreModule
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val fp_data_hazard_wb = wb_ctrl.wfd && checkHazards(fp_hazard_targets, _ === wb_waddr)
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val id_wb_hazard = wb_reg_valid && (data_hazard_wb && wb_set_sboard || fp_data_hazard_wb)
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val id_stall_fpu = if (!params(BuildFPU).isEmpty) {
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val id_stall_fpu = if (usingFPU) {
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val fp_sboard = new Scoreboard(32)
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fp_sboard.set((wb_dcache_miss && wb_ctrl.wfd || io.fpu.sboard_set) && wb_valid, wb_waddr)
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fp_sboard.clear(dmem_resp_replay && dmem_resp_fpu, dmem_resp_waddr)
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@ -436,7 +442,7 @@ class Rocket extends CoreModule
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id_ex_hazard || id_mem_hazard || id_wb_hazard || id_sboard_hazard ||
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id_ctrl.fp && id_stall_fpu ||
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id_ctrl.mem && !io.dmem.req.ready ||
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Bool(!params(BuildRoCC).isEmpty) && wb_reg_rocc_pending && id_ctrl.rocc && !io.rocc.cmd.ready ||
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Bool(usingRoCC) && wb_reg_rocc_pending && id_ctrl.rocc && !io.rocc.cmd.ready ||
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id_do_fence ||
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csr.io.csr_stall
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ctrl_killd := !io.imem.resp.valid || take_pc || ctrl_stalld || csr.io.interrupt
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@ -488,7 +494,7 @@ class Rocket extends CoreModule
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io.dmem.req.bits.addr := Cat(vaSign(ex_rs(0), alu.io.adder_out), alu.io.adder_out(vaddrBits-1,0)).toUInt
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io.dmem.req.bits.tag := Cat(ex_waddr, ex_ctrl.fp)
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io.dmem.req.bits.data := Mux(mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2)
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require(params(CoreDCacheReqTagBits) >= 6)
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require(p(CoreDCacheReqTagBits) >= 6)
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io.dmem.invalidate_lr := wb_xcpt
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io.rocc.cmd.valid := wb_rocc_val
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@ -498,7 +504,7 @@ class Rocket extends CoreModule
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io.rocc.cmd.bits.rs1 := wb_reg_wdata
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io.rocc.cmd.bits.rs2 := wb_reg_rs2
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if (EnableCommitLog) {
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if (enableCommitLog) {
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val pc = Wire(SInt(width=64))
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pc := wb_reg_pc
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val inst = wb_reg_inst
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