Removed all traces of params

rocket/src/main/scala/icache.scala

@@ -4,148 +4,25 @@ import Chisel._
 import uncore._
 import Util._
 
-abstract trait L1CacheParameters extends CacheParameters with CoreParameters {
-  val outerDataBeats = params(TLDataBeats)
-  val outerDataBits = params(TLDataBits)
+trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters {
+  val outerDataBeats = p(TLDataBeats)
+  val outerDataBits = p(TLDataBits)
   val refillCyclesPerBeat = outerDataBits/rowBits
   val refillCycles = refillCyclesPerBeat*outerDataBeats
 }
 
-abstract trait FrontendParameters extends L1CacheParameters
-abstract class FrontendBundle extends Bundle with FrontendParameters
-abstract class FrontendModule extends Module with FrontendParameters
-
-class FrontendReq extends CoreBundle {
-  val pc = UInt(width = vaddrBitsExtended)
-}
-
-class FrontendResp extends CoreBundle {
-  val pc = UInt(width = vaddrBitsExtended)  // ID stage PC
-  val data = Vec(Bits(width = coreInstBits), coreFetchWidth)
-  val mask = Bits(width = coreFetchWidth)
-  val xcpt_if = Bool()
-}
-
-class CPUFrontendIO extends CoreBundle {
-  val req = Valid(new FrontendReq)
-  val resp = Decoupled(new FrontendResp).flip
-  val btb_resp = Valid(new BTBResp).flip
-  val btb_update = Valid(new BTBUpdate)
-  val bht_update = Valid(new BHTUpdate)
-  val ras_update = Valid(new RASUpdate)
-  val invalidate = Bool(OUTPUT)
-  val npc = UInt(INPUT, width = vaddrBitsExtended)
-}
-
-class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
-{
-  val io = new Bundle {
-    val cpu = new CPUFrontendIO().flip
-    val ptw = new TLBPTWIO()
-    val mem = new ClientUncachedTileLinkIO
-  }
-
-  val btb = Module(new BTB(btb_updates_out_of_order))
-  val icache = Module(new ICache)
-  val tlb = Module(new TLB)
-
-  val s1_pc_ = Reg(UInt())
-  val s1_pc = ~(~s1_pc_ | (coreInstBytes-1)) // discard PC LSBS (this propagates down the pipeline)
-  val s1_same_block = Reg(Bool())
-  val s2_valid = Reg(init=Bool(true))
-  val s2_pc = Reg(init=UInt(START_ADDR))
-  val s2_btb_resp_valid = Reg(init=Bool(false))
-  val s2_btb_resp_bits = Reg(btb.io.resp.bits)
-  val s2_xcpt_if = Reg(init=Bool(false))
-
-  val msb = vaddrBits-1
-  val lsb = log2Up(coreFetchWidth*coreInstBytes)
-  val btbTarget = Cat(btb.io.resp.bits.target(msb), btb.io.resp.bits.target)
-  val ntpc_0 = s1_pc + UInt(coreInstBytes*coreFetchWidth)
-  val ntpc = Cat(s1_pc(msb) & ntpc_0(msb), ntpc_0(msb,lsb), Bits(0,lsb)) // unsure
-  val icmiss = s2_valid && !icache.io.resp.valid
-  val predicted_npc = Mux(btb.io.resp.bits.taken, btbTarget, ntpc)
-  val npc = Mux(icmiss, s2_pc, predicted_npc).toUInt
-  val s0_same_block = !icmiss && !io.cpu.req.valid && !btb.io.resp.bits.taken && ((ntpc & rowBytes) === (s1_pc & rowBytes))
-
-  val stall = io.cpu.resp.valid && !io.cpu.resp.ready
-  when (!stall) {
-    s1_same_block := s0_same_block && !tlb.io.resp.miss
-    s1_pc_ := npc
-    s2_valid := !icmiss
-    when (!icmiss) {
-      s2_pc := s1_pc
-      s2_btb_resp_valid := btb.io.resp.valid
-      when (btb.io.resp.valid) { s2_btb_resp_bits := btb.io.resp.bits }
-      s2_xcpt_if := tlb.io.resp.xcpt_if
-    }
-  }
-  when (io.cpu.req.valid) {
-    s1_same_block := Bool(false)
-    s1_pc_ := io.cpu.req.bits.pc
-    s2_valid := Bool(false)
-  }
-
-  btb.io.req.valid := !stall && !icmiss
-  btb.io.req.bits.addr := s1_pc
-  btb.io.btb_update := io.cpu.btb_update
-  btb.io.bht_update := io.cpu.bht_update
-  btb.io.ras_update := io.cpu.ras_update
-  btb.io.invalidate := io.cpu.invalidate || io.ptw.invalidate
-
-  io.ptw <> tlb.io.ptw
-  tlb.io.req.valid := !stall && !icmiss
-  tlb.io.req.bits.vpn := s1_pc >> pgIdxBits
-  tlb.io.req.bits.asid := UInt(0)
-  tlb.io.req.bits.passthrough := Bool(false)
-  tlb.io.req.bits.instruction := Bool(true)
-  tlb.io.req.bits.store := Bool(false)
-
-  io.mem <> icache.io.mem
-  icache.io.req.valid := !stall && !s0_same_block
-  icache.io.req.bits.idx := io.cpu.npc
-  icache.io.invalidate := io.cpu.invalidate
-  icache.io.req.bits.ppn := tlb.io.resp.ppn
-  icache.io.req.bits.kill := io.cpu.req.valid ||
-    tlb.io.resp.miss || tlb.io.resp.xcpt_if ||
-    icmiss || io.ptw.invalidate
-  icache.io.resp.ready := !stall && !s1_same_block
-
-  io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icache.io.resp.valid)
-  io.cpu.resp.bits.pc := s2_pc
-  io.cpu.npc := Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)
-
-  require(coreFetchWidth * coreInstBytes <= rowBytes)
-  val fetch_data =
-    if (coreFetchWidth * coreInstBytes == rowBytes) icache.io.resp.bits.datablock
-    else icache.io.resp.bits.datablock >> (s2_pc(log2Up(rowBytes)-1,log2Up(coreFetchWidth*coreInstBytes)) << log2Up(coreFetchWidth*coreInstBits))
-
-  for (i <- 0 until coreFetchWidth) {
-    io.cpu.resp.bits.data(i) := fetch_data(i*coreInstBits+coreInstBits-1, i*coreInstBits)
-  }
-
-  val all_ones = UInt((1 << (coreFetchWidth+1))-1)
-  val msk_pc = if (coreFetchWidth == 1) all_ones else all_ones << s2_pc(log2Up(coreFetchWidth) -1+2,2)
-  io.cpu.resp.bits.mask := Mux(s2_btb_resp_valid, msk_pc & s2_btb_resp_bits.mask, msk_pc)
-  io.cpu.resp.bits.xcpt_if := s2_xcpt_if
-
-  io.cpu.btb_resp.valid := s2_btb_resp_valid
-  io.cpu.btb_resp.bits := s2_btb_resp_bits
-}
-
-class ICacheReq extends FrontendBundle {
+class ICacheReq(implicit p: Parameters) extends CoreBundle()(p) {
   val idx = UInt(width = pgIdxBits)
   val ppn = UInt(width = ppnBits) // delayed one cycle
   val kill = Bool() // delayed one cycle
 }
 
-class ICacheResp extends FrontendBundle {
+class ICacheResp(implicit p: Parameters) extends CoreBundle()(p) with HasL1CacheParameters {
   val data = Bits(width = coreInstBits)
   val datablock = Bits(width = rowBits)
 }
 
-class ICache extends FrontendModule
-{
+class ICache(implicit p: Parameters) extends CoreModule()(p) with HasL1CacheParameters {
   val io = new Bundle {
     val req = Valid(new ICacheReq).flip
     val resp = Decoupled(new ICacheResp)