more itlb/dtlb/ptw fixes
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@ -67,8 +67,9 @@ class ioCtrlAll extends Bundle()
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val imem = new ioImem(List("req_val", "req_rdy", "resp_val")).flip();
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val dmem = new ioDmem(List("req_val", "req_rdy", "req_cmd", "req_type", "resp_miss")).flip();
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val host = new ioHost(List("start"));
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val dtlb_busy = Bool('input);
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val dtlb_miss = Bool('input);
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val itlb_miss = Bool('input);
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// val itlb_miss = Bool('input);
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val xcpt_dtlb_ld = Bool('input);
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val xcpt_dtlb_st = Bool('input);
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val xcpt_itlb = Bool('input);
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@ -497,7 +498,7 @@ class rocketCtrl extends Component
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id_ren1 & id_stall_raddr1 |
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(id_sel_wa === WA_RD) & id_stall_waddr |
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(id_sel_wa === WA_RA) & id_stall_ra |
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id_mem_val & ~io.dmem.req_rdy |
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id_mem_val & (~io.dmem.req_rdy | io.dtlb_busy) |
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id_sync & ~io.dmem.req_rdy |
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id_console_out_val & ~io.console.rdy |
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id_div_val & ~io.dpath.div_rdy |
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@ -513,7 +514,8 @@ class rocketCtrl extends Component
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io.dpath.stalld := ctrl_stalld.toBool;
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io.dpath.killf := take_pc | io.itlb_miss | ~io.imem.resp_val;
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// io.dpath.killf := take_pc | io.itlb_miss | ~io.imem.resp_val;
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io.dpath.killf := take_pc | ~io.imem.resp_val;
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io.dpath.killd := ctrl_killd.toBool;
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io.dpath.killx := kill_ex.toBool;
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io.dpath.killm := kill_mem.toBool;
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