From 834bcf6b7e195be730aef74a78ffad3f8f30b397 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Thu, 29 Jun 2017 19:35:15 -0700 Subject: [PATCH] PLIC: simplify some scala code --- src/main/scala/uncore/devices/Plic.scala | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/main/scala/uncore/devices/Plic.scala b/src/main/scala/uncore/devices/Plic.scala index 96451a08..e2d31927 100644 --- a/src/main/scala/uncore/devices/Plic.scala +++ b/src/main/scala/uncore/devices/Plic.scala @@ -177,12 +177,10 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule } val claimer = Wire(init = Vec.fill(nHarts){Bool(false)}) - val claiming = Wire(init = Vec.tabulate(nHarts){i => Mux(claimer(i), UIntToOH(maxDevs(i)), UInt(0, width=log2Up(nDevices+1)))}) + val claiming = Wire(init = Vec.tabulate(nHarts){i => Mux(claimer(i), UIntToOH(maxDevs(i)), UInt(0))}) val claimedDevs = Wire(init = Vec(claiming.reduceLeft( _ | _ ).toBools)) - for ((pg, c) <- (pending zip gateways) zip claimedDevs) { - val p = pg._1 - val g = pg._2 + for ((p, g), c) <- (pending zip gateways) zip claimedDevs) { g.ready := !p g.complete := false when(c) {