From 834307063943ae5398ce8ecf63c3979aa379fa57 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 2 Sep 2016 22:48:00 -0700 Subject: [PATCH] tilelink2: detect 1-bit overflow in register definitions --- src/main/scala/uncore/tilelink2/RegMapper.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/uncore/tilelink2/RegMapper.scala b/src/main/scala/uncore/tilelink2/RegMapper.scala index d3f7a559..033d507b 100644 --- a/src/main/scala/uncore/tilelink2/RegMapper.scala +++ b/src/main/scala/uncore/tilelink2/RegMapper.scala @@ -85,7 +85,7 @@ object RegMapper val (reg, low, field) = flat(i) val high = low + field.width - 1 // Confirm that no register is too big - require (high <= 8*bytes) + require (high < 8*bytes) val rimask = frontMask(high, low).orR() val wimask = frontMask(high, low).andR() val romask = backMask(high, low).orR()