riscv/rocket-chip
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Fix toBits/toUInt/toSInt deprecation warnings

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This commit is contained in:
Andrew Waterman
2016-07-31 17:13:52 -07:00
parent a6e009d8de
commit 832e56d3c7
36 changed files with 188 additions and 171 deletions
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2
uncore/src/main/scala/tilelink/Arbiters.scala
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@ -144,7 +144,7 @@ trait AppendsArbiterId extends TileLinkArbiterLike {
else
UInt(0)
}
def arbIdx(in: ManagerSourcedWithId) = in.client_xact_id(log2Up(arbN)-1,0).toUInt
def arbIdx(in: ManagerSourcedWithId) = in.client_xact_id(log2Up(arbN)-1,0)
}
/** Uses the client_xact_id as is (assumes it has been set to port index) */

2
uncore/src/main/scala/tilelink/Definitions.scala
View File

@ -397,7 +397,7 @@ object Acquire {
Acquire.putPrefetchType -> Cat(M_XWR, alloc)))
}
def fullWriteMask(implicit p: Parameters) = SInt(-1, width = p(TLKey(p(TLId))).writeMaskBits).toUInt
def fullWriteMask(implicit p: Parameters) = SInt(-1, width = p(TLKey(p(TLId))).writeMaskBits).asUInt
// Most generic constructor
def apply(