riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Fix toBits/toUInt/toSInt deprecation warnings

Browse Source
This commit is contained in:
Andrew Waterman
2016-07-31 17:13:52 -07:00
parent a6e009d8de
commit 832e56d3c7
36 changed files with 188 additions and 171 deletions
Download Patch File Download Diff File Expand all files Collapse all files

25
uncore/src/main/scala/devices/Debug.scala
View File

@ -224,14 +224,11 @@ case class DebugModuleConfig (
val hasHaltSum = (nComponents > 64) || (nSerialPorts > 0)
val hasDebugRom = debugRomContents match{
case Some(_) => true
case None => false
}
val hasDebugRom = debugRomContents.nonEmpty
if (hasDebugRom) {
require (debugRomContents.size > 0)
require (debugRomContents.size <= 512)
require (debugRomContents.get.size > 0)
require (debugRomContents.get.size <= 512)
}
require (nNDResetCycles > 0)
@ -647,15 +644,15 @@ class DebugModule ()(implicit val p:cde.Parameters)
sbRamRdData := ramRdData
ramWrMask := Mux(sbRamWrEn, sbWrMask, dbRamWrMask.toBits())
ramWrMask := Mux(sbRamWrEn, sbWrMask, dbRamWrMask.asUInt)
assert (!((dbRamWrEn | dbRamRdEn) & (sbRamRdEn | sbRamWrEn)), "Stall logic should have prevented concurrent SB/DB RAM Access")
// Make copies of DB RAM data before writing.
val dbRamWrDataVec = Fill(1 << (dbRamAddrWidth - ramAddrWidth), dbRamWrData)
ramWrData := Mux(sbRamWrEn,
(ramWrMask & sbRamWrData ) | (~ramWrMask & ramRdData),
(ramWrMask & dbRamWrDataVec.toBits) | (~ramWrMask & ramRdData))
(ramWrMask & sbRamWrData ) | (~ramWrMask & ramRdData),
(ramWrMask & dbRamWrDataVec) | (~ramWrMask & ramRdData))
ramAddr := Mux(sbRamWrEn | sbRamRdEn, sbRamAddr,
dbRamAddr >> (dbRamAddrWidth - ramAddrWidth))
@ -700,7 +697,7 @@ class DebugModule ()(implicit val p:cde.Parameters)
// haltnot handled in other logic
if (cfg.hasBusMaster){
// buserror is set 'until 0 is written to any bit in this field'.
CONTROLReg.buserror := Mux((CONTROLWrData.buserror === SInt(-1).toBits), CONTROLReg.buserror, UInt(0))
CONTROLReg.buserror := Mux(CONTROLWrData.buserror.andR, CONTROLReg.buserror, UInt(0))
CONTROLReg.autoincrement := CONTROLWrData.autoincrement
CONTROLReg.access := CONTROLWrData.access
}
@ -743,15 +740,15 @@ class DebugModule ()(implicit val p:cde.Parameters)
dbRamRdEn := Bool(false)
when ((dbReq.addr >> 4) === Bits(0)) { // 0x00 - 0x0F Debug RAM
dbRdData := RAMRdData.toBits()
dbRdData := RAMRdData.asUInt
dbRamRdEn := dbRdEn
}.elsewhen (dbReq.addr === DMCONTROL) {
dbRdData := CONTROLRdData.toBits()
dbRdData := CONTROLRdData.asUInt
}.elsewhen (dbReq.addr === DMINFO) {
dbRdData := DMINFORdData.toBits()
dbRdData := DMINFORdData.asUInt
}.elsewhen (dbReq.addr === HALTSUM) {
if (cfg.hasHaltSum){
dbRdData := HALTSUMRdData.toBits()
dbRdData := HALTSUMRdData.asUInt
} else {
dbRdData := UInt(0)
}

25
uncore/src/main/scala/devices/Dma.scala
View File

@ -5,6 +5,7 @@ import cde.{Parameters, Field}
import junctions._
import junctions.NastiConstants._
import uncore.tilelink._
import uncore.Util._
case object NDmaTransactors extends Field[Int]
case object NDmaXacts extends Field[Int]
@ -104,7 +105,7 @@ class DmaManager(outstandingCSR: Int)(implicit p: Parameters)
val ctrl_regs = Reg(Vec(nCtrlWords, UInt(width = nastiXDataBits)))
val ctrl_idx = Reg(UInt(width = log2Up(nCtrlWords)))
val ctrl_done = Reg(Bool())
val ctrl_blob = ctrl_regs.toBits
val ctrl_blob = ctrl_regs.asUInt
val ctrl_id = Reg(UInt(width = nastiXIdBits))
val sizeOffset = 3 * addrBits
@ -228,7 +229,7 @@ class DmaTrackerFile(implicit p: Parameters) extends DmaModule()(p) {
}
val trackers = List.fill(nDmaTransactors) { Module(new DmaTracker) }
val reqReadys = Vec(trackers.map(_.io.dma.req.ready)).toBits
val reqReadys = trackers.map(_.io.dma.req.ready).asUInt
io.mem <> trackers.map(_.io.mem)
io.mmio <> trackers.map(_.io.mmio)
@ -305,10 +306,10 @@ class DmaTracker(implicit p: Parameters) extends DmaModule()(p)
val (put_beat, put_done) = Counter(
io.mem.acquire.fire() && acq.hasData(), tlDataBeats)
val put_mask = Vec.tabulate(tlDataBytes) { i =>
val put_mask = Seq.tabulate(tlDataBytes) { i =>
val byte_index = Cat(put_beat, UInt(i, tlByteAddrBits))
byte_index >= offset && byte_index < bytes_left
}.toBits
}.asUInt
val prefetch_sent = io.mem.acquire.fire() && io.mem.acquire.bits.isPrefetch()
val prefetch_busy = Reg(init = UInt(0, tlMaxClientXacts))
@ -324,14 +325,14 @@ class DmaTracker(implicit p: Parameters) extends DmaModule()(p)
(value >> sel)(0)
when (alignment === UInt(0)) {
put_data := data_buffer.read(base_index)
put_data := data_buffer(base_index)
} .elsewhen (shift_dir) {
val shift_index = base_index - beat_align
when (bit_align === UInt(0)) {
put_data := data_buffer.read(shift_index)
put_data := data_buffer(shift_index)
} .otherwise {
val upper_bits = data_buffer.read(shift_index)
val lower_bits = data_buffer.read(shift_index - UInt(1))
val upper_bits = data_buffer(shift_index)
val lower_bits = data_buffer(shift_index - UInt(1))
val upper_shifted = upper_bits << bit_align
val lower_shifted = lower_bits >> rev_align
put_data := upper_shifted | lower_shifted
@ -339,10 +340,10 @@ class DmaTracker(implicit p: Parameters) extends DmaModule()(p)
} .otherwise {
val shift_index = base_index + beat_align
when (bit_align === UInt(0)) {
put_data := data_buffer.read(shift_index)
put_data := data_buffer(shift_index)
} .otherwise {
val upper_bits = data_buffer.read(shift_index + UInt(1))
val lower_bits = data_buffer.read(shift_index)
val upper_bits = data_buffer(shift_index + UInt(1))
val lower_bits = data_buffer(shift_index)
val upper_shifted = upper_bits << rev_align
val lower_shifted = lower_bits >> bit_align
put_data := upper_shifted | lower_shifted
@ -502,7 +503,7 @@ class DmaTracker(implicit p: Parameters) extends DmaModule()(p)
val write_half = gnt.client_xact_id(0)
val write_idx = Cat(write_half, gnt.addr_beat)
get_inflight := get_inflight & ~UIntToOH(write_idx)
data_buffer.write(write_idx, gnt.data)
data_buffer(write_idx) := gnt.data
} .otherwise {
put_inflight := Bool(false)
}

2
uncore/src/main/scala/devices/Plic.scala
View File

@ -154,7 +154,7 @@ class PLIC(val cfg: PLICConfig)(implicit val p: Parameters) extends Module
val word =
if (tlDataBytes >= pending.size) UInt(0)
else addr(log2Up(pending.size)-1,log2Up(tlDataBytes))
rdata := pending.toBits >> (word * tlDataBits)
rdata := pending.asUInt >> (word * tlDataBits)
}.otherwise {
val regsPerBeat = tlDataBytes >> log2Up(cfg.priorityBytes)
val word =