Fix toBits/toUInt/toSInt deprecation warnings

uncore/src/main/scala/agents/Agents.scala

@@ -8,6 +8,7 @@ import junctions._
 import uncore.tilelink._
 import uncore.converters._
 import uncore.coherence._
+import uncore.Util._
 
 case object NReleaseTransactors extends Field[Int]
 case object NProbeTransactors extends Field[Int]
@@ -59,7 +60,7 @@ trait HasCoherenceAgentWiringHelpers {
     val idx = in.bits.manager_xact_id
     outs.map(_.bits := in.bits)
     outs.zipWithIndex.map { case (o,i) => o.valid := in.valid && idx === UInt(i) }
-    in.ready := Vec(outs.map(_.ready)).read(idx)
+    in.ready := outs.map(_.ready).apply(idx)
   }
 
   /** Broadcasts valid messages on this channel to all trackers,
@@ -82,10 +83,10 @@ trait HasCoherenceAgentWiringHelpers {
         dataOverrides: Option[Seq[UInt]] = None,
         allocOverride: Option[Bool] = None,
         matchOverride: Option[Bool] = None) {
-    val ready_bits = Vec(outs.map(_.ready)).toBits
-    val can_alloc_bits = Vec(allocs.map(_.can)).toBits
+    val ready_bits = outs.map(_.ready).asUInt
+    val can_alloc_bits = allocs.map(_.can).asUInt
     val should_alloc_bits = PriorityEncoderOH(can_alloc_bits)
-    val match_bits = Vec(allocs.map(_.matches)).toBits
+    val match_bits = allocs.map(_.matches).asUInt
     val no_matches = !match_bits.orR
     val alloc_ok = allocOverride.getOrElse(Bool(true))
     val match_ok = matchOverride.getOrElse(Bool(true))

uncore/src/main/scala/agents/Cache.scala

@@ -151,9 +151,9 @@ class MetadataArray[T <: Metadata](onReset: () => T)(implicit p: Parameters) ext
   val rst_cnt = Reg(init=UInt(0, log2Up(nSets+1)))
   val rst = rst_cnt < UInt(nSets)
   val waddr = Mux(rst, rst_cnt, io.write.bits.idx)
-  val wdata = Mux(rst, rstVal, io.write.bits.data).toBits
-  val wmask = Mux(rst || Bool(nWays == 1), SInt(-1), io.write.bits.way_en.toSInt).toBools
-  val rmask = Mux(rst || Bool(nWays == 1), SInt(-1), io.read.bits.way_en.toSInt).toBools
+  val wdata = Mux(rst, rstVal, io.write.bits.data).asUInt
+  val wmask = Mux(rst || Bool(nWays == 1), SInt(-1), io.write.bits.way_en.asSInt).toBools
+  val rmask = Mux(rst || Bool(nWays == 1), SInt(-1), io.read.bits.way_en.asSInt).toBools
   when (rst) { rst_cnt := rst_cnt+UInt(1) }
 
   val metabits = rstVal.getWidth
@@ -161,21 +161,18 @@ class MetadataArray[T <: Metadata](onReset: () => T)(implicit p: Parameters) ext
   if (hasSplitMetadata) {
     val tag_arrs = List.fill(nWays){ SeqMem(nSets, UInt(width = metabits)) }
     val tag_readout = Wire(Vec(nWays,rstVal.cloneType))
-    val tags_vec = Wire(Vec(nWays, UInt(width = metabits)))
     (0 until nWays).foreach { (i) =>
       when (rst || (io.write.valid && wmask(i))) {
         tag_arrs(i).write(waddr, wdata)
       }
-      tags_vec(i) := tag_arrs(i).read(io.read.bits.idx, io.read.valid && rmask(i))
+      io.resp(i) := rstVal.fromBits(tag_arrs(i).read(io.read.bits.idx, io.read.valid && rmask(i)))
     }
-    io.resp := io.resp.fromBits(tags_vec.toBits)
   } else {
     val tag_arr = SeqMem(nSets, Vec(nWays, UInt(width = metabits)))
     when (rst || io.write.valid) {
       tag_arr.write(waddr, Vec.fill(nWays)(wdata), wmask)
     }
-    val tags = tag_arr.read(io.read.bits.idx, io.read.valid).toBits
-    io.resp := io.resp.fromBits(tags)
+    io.resp := tag_arr.read(io.read.bits.idx, io.read.valid).map(rstVal.fromBits(_))
   }
 
   io.read.ready := !rst && !io.write.valid // so really this could be a 6T RAM
@@ -329,7 +326,7 @@ class L2MetadataArray(implicit p: Parameters) extends L2HellaCacheModule()(p) {
   val meta = Module(new MetadataArray(onReset _))
   meta.io.read <> io.read
   meta.io.write <> io.write
-  val way_en_1h = (Vec.fill(nWays){Bool(true)}).toBits
+  val way_en_1h = UInt((BigInt(1) << nWays) - 1)
   val s1_way_en_1h = RegEnable(way_en_1h, io.read.valid)
   meta.io.read.bits.way_en := way_en_1h
 
@@ -338,7 +335,7 @@ class L2MetadataArray(implicit p: Parameters) extends L2HellaCacheModule()(p) {
   def wayMap[T <: Data](f: Int => T) = Vec((0 until nWays).map(f))
   val s1_clk_en = Reg(next = io.read.fire())
   val s1_tag_eq_way = wayMap((w: Int) => meta.io.resp(w).tag === s1_tag)
-  val s1_tag_match_way = wayMap((w: Int) => s1_tag_eq_way(w) && meta.io.resp(w).coh.outer.isValid() && s1_way_en_1h(w).toBool).toBits
+  val s1_tag_match_way = wayMap((w: Int) => s1_tag_eq_way(w) && meta.io.resp(w).coh.outer.isValid() && s1_way_en_1h(w).toBool).asUInt
   val s1_idx = RegEnable(io.read.bits.idx, io.read.valid) // deal with stalls?
   val s2_tag_match_way = RegEnable(s1_tag_match_way, s1_clk_en)
   val s2_tag_match = s2_tag_match_way.orR
@@ -445,7 +442,7 @@ class L2DataArray(delay: Int)(implicit p: Parameters) extends L2HellaCacheModule
 
   val r_req = Pipe(io.read.fire(), io.read.bits)
   io.resp := Pipe(r_req.valid, r_req.bits, delay)
-  io.resp.bits.data := Pipe(r_req.valid, array.read(raddr, ren).toBits, delay).bits
+  io.resp.bits.data := Pipe(r_req.valid, array.read(raddr, ren).asUInt, delay).bits
   io.read.ready := !io.write.valid
   io.write.ready := Bool(true)
 }

uncore/src/main/scala/agents/Ecc.scala

@@ -3,6 +3,7 @@
 package uncore.agents
 
 import Chisel._
+import uncore.Util._
 
 abstract class Decoding
 {
@@ -63,24 +64,23 @@ class SECCode extends Code
       } else
         x(mapping(i))
     }
-    Vec(y).toBits
+    y.asUInt
   }
   def decode(y: UInt) = new Decoding {
     val n = y.getWidth
     require(n > 0 && !isPow2(n))
 
     val p2 = for (i <- 0 until log2Up(n)) yield 1 << i
-    val syndrome = p2 map { i =>
+    val syndrome = (p2 map { i =>
       val r = for (j <- 1 to n; if (j & i) != 0)
         yield y(j-1)
       r reduce (_^_)
-    }
-    val s = Vec(syndrome).toBits
+    }).asUInt
 
-    private def swizzle(z: UInt) = Vec((1 to n).filter(i => !isPow2(i)).map(i => z(i-1))).toBits
+    private def swizzle(z: UInt) = (1 to n).filter(i => !isPow2(i)).map(i => z(i-1)).asUInt
     def uncorrected = swizzle(y)
-    def corrected = swizzle(((y.toUInt << 1) ^ UIntToOH(s)) >> 1)
-    def correctable = s.orR
+    def corrected = swizzle(((y << 1) ^ UIntToOH(syndrome)) >> 1)
+    def correctable = syndrome.orR
     def uncorrectable = Bool(false)
   }
   private def mapping(i: Int) = i-1-log2Up(i)

uncore/src/main/scala/agents/StoreDataQueue.scala

@@ -52,7 +52,7 @@ trait HasStoreDataQueue extends HasStoreDataQueueParameters {
                 ).reduce(_||_)
 
   lazy val sdqLoc = List.fill(nTransactors) {
-    DataQueueLocation(sdq_alloc_id, inStoreQueue).toBits
+    DataQueueLocation(sdq_alloc_id, inStoreQueue).asUInt
   }
 
   /*
@@ -74,7 +74,7 @@ trait HasStoreDataQueue extends HasStoreDataQueueParameters {
   lazy val vwbqLoc = (0 until nTransactors).map(i =>
     (DataQueueLocation(rel_data_cnt,
                        (if(i < nReleaseTransactors) inVolWBQueue
-                        else inClientReleaseQueue)).toBits))
+                        else inClientReleaseQueue)).asUInt))
   /*
   doInputRoutingWithAllocation(
     io.inner.release,

uncore/src/main/scala/agents/Trackers.scala

@@ -380,7 +380,7 @@ trait EmitsInnerProbes extends HasBlockAddressBuffer
   def full_representation: UInt
   def initializeProbes() {
     if (needs_probes)
-      pending_iprbs := full_representation & ~io.incoherent.toBits
+      pending_iprbs := full_representation & ~io.incoherent.asUInt
     else
       pending_iprbs := UInt(0)
   }