Fix toBits/toUInt/toSInt deprecation warnings
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@ -467,12 +467,12 @@ class HastiTestSRAM(depth: Int)(implicit p: Parameters) extends HastiModule()(p)
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val mask_decode = Vec.tabulate(hastiAlignment+1) (UInt(_) <= io.hsize)
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val mask_wide = Vec.tabulate(hastiDataBytes) { i => mask_decode(log2Up(i+1)) }
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val mask_shift = if (hastiAlignment == 0) UInt(1) else
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mask_wide.toBits().asUInt() << io.haddr(hastiAlignment-1,0)
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mask_wide.asUInt() << io.haddr(hastiAlignment-1,0)
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// The request had better have been aligned! (AHB-lite requires this)
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if (hastiAlignment >= 1) {
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assert (io.htrans === HTRANS_IDLE || io.htrans === HTRANS_BUSY ||
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(io.haddr & mask_decode.toBits()(hastiAlignment,1).asUInt) === UInt(0),
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(io.haddr & mask_decode.asUInt()(hastiAlignment,1)) === UInt(0),
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"HASTI request not aligned")
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}
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@ -543,7 +543,7 @@ class HastiTestSRAM(depth: Int)(implicit p: Parameters) extends HastiModule()(p)
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map { case (m, p) => Mux(d_read && ready && m, p, Bits(0)) })
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// Finally, the outputs
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io.hrdata := outdata.toBits()
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io.hrdata := outdata.asUInt
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io.hready := ready
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io.hresp := HRESP_OKAY
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}
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