diff --git a/uncore/src/main/scala/cache.scala b/uncore/src/main/scala/cache.scala index 3de8ba4a..ca6b5c3f 100644 --- a/uncore/src/main/scala/cache.scala +++ b/uncore/src/main/scala/cache.scala @@ -212,13 +212,14 @@ class L2DataArray extends L2HellaCacheModule { io.write.ready := Bool(true) } -class L2HellaCache(bankId: Int) extends CoherenceAgent with L2HellaCacheParameters { +class L2HellaCache(bankId: Int, innerId: String, outerId: String) extends + CoherenceAgent(innerId, outerId) with L2HellaCacheParameters { require(isPow2(nSets)) require(isPow2(nWays)) require(refillCycles == 1) - val tshrfile = Module(new TSHRFile(bankId)) + val tshrfile = Module(new TSHRFile(bankId, innerId, outerId)) val meta = Module(new L2MetadataArray) val data = Module(new L2DataArray) @@ -234,10 +235,10 @@ class L2HellaCache(bankId: Int) extends CoherenceAgent with L2HellaCacheParamete } -class TSHRFile(bankId: Int) extends L2HellaCacheModule { +class TSHRFile(bankId: Int, innerId: String, outerId: String) extends L2HellaCacheModule { val io = new Bundle { - val inner = (new TileLinkIO).flip - val outer = new UncachedTileLinkIO + val inner = Bundle(new TileLinkIO, {case TLId => innerId}).flip + val outer = Bundle(new UncachedTileLinkIO, {case TLId => outerId}) val incoherent = Vec.fill(nClients){Bool()}.asInput val meta_read = Decoupled(new L2MetaReadReq) val meta_write = Decoupled(new L2MetaWriteReq) @@ -261,9 +262,9 @@ class TSHRFile(bankId: Int) extends L2HellaCacheModule { // Create TSHRs for outstanding transactions val trackerList = (0 until nReleaseTransactors).map { id => - Module(new L2VoluntaryReleaseTracker(id, bankId)) + Module(new L2VoluntaryReleaseTracker(id, bankId, innerId, outerId)) } ++ (nReleaseTransactors until nTransactors).map { id => - Module(new L2AcquireTracker(id, bankId)) + Module(new L2AcquireTracker(id, bankId, innerId, outerId)) } // Propagate incoherence flags @@ -312,7 +313,8 @@ class TSHRFile(bankId: Int) extends L2HellaCacheModule { ack.ready := Bool(true) // Arbitrate for the outer memory port - val outer_arb = Module(new UncachedTileLinkIOArbiterThatPassesId(trackerList.size)) + val outer_arb = Module(new UncachedTileLinkIOArbiterThatPassesId(trackerList.size), + {case TLId => outerId}) outer_arb.io.in zip trackerList map { case(arb, t) => arb <> t.io.outer } io.outer <> outer_arb.io.out @@ -327,10 +329,10 @@ class TSHRFile(bankId: Int) extends L2HellaCacheModule { } -abstract class L2XactTracker extends L2HellaCacheModule { +abstract class L2XactTracker(innerId: String, outerId: String) extends L2HellaCacheModule { val io = new Bundle { - val inner = (new TileLinkIO).flip - val outer = new UncachedTileLinkIO + val inner = Bundle(new TileLinkIO, {case TLId => innerId}).flip + val outer = Bundle(new UncachedTileLinkIO, {case TLId => outerId}) val tile_incoherent = Bits(INPUT, nClients) val has_acquire_conflict = Bool(OUTPUT) val has_release_conflict = Bool(OUTPUT) @@ -350,7 +352,7 @@ abstract class L2XactTracker extends L2HellaCacheModule { } -class L2VoluntaryReleaseTracker(trackerId: Int, bankId: Int) extends L2XactTracker { +class L2VoluntaryReleaseTracker(trackerId: Int, bankId: Int, innerId: String, outerId: String) extends L2XactTracker(innerId, outerId) { val s_idle :: s_mem :: s_ack :: s_busy :: Nil = Enum(UInt(), 4) val state = Reg(init=s_idle) val xact = Reg{ new Release } @@ -364,10 +366,11 @@ class L2VoluntaryReleaseTracker(trackerId: Int, bankId: Int) extends L2XactTrack io.outer.grant.ready := Bool(false) io.outer.acquire.valid := Bool(false) io.outer.acquire.bits.header.src := UInt(bankId) - io.outer.acquire.bits.payload := Acquire(co.getUncachedWriteAcquireType, + io.outer.acquire.bits.payload := Bundle(Acquire(co.getUncachedWriteAcquireType, xact.addr, UInt(trackerId), - xact.data) + xact.data), + { case TLId => outerId }) io.inner.acquire.ready := Bool(false) io.inner.probe.valid := Bool(false) io.inner.release.ready := Bool(false) @@ -426,7 +429,7 @@ class L2VoluntaryReleaseTracker(trackerId: Int, bankId: Int) extends L2XactTrack } } -class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker { +class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: String) extends L2XactTracker(innerId, outerId) { val s_idle :: s_probe :: s_mem_read :: s_mem_write :: s_make_grant :: s_busy :: Nil = Enum(UInt(), 6) val state = Reg(init=s_idle) val xact = Reg{ new Acquire } @@ -440,11 +443,14 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker { val pending_outer_write = co.messageHasData(xact) val pending_outer_read = co.requiresOuterRead(xact.a_type) - val outer_write_acq = Acquire(co.getUncachedWriteAcquireType, - xact.addr, UInt(trackerId), xact.data) - val outer_write_rel = Acquire(co.getUncachedWriteAcquireType, - xact.addr, UInt(trackerId), c_rel.payload.data) - val outer_read = Acquire(co.getUncachedReadAcquireType, xact.addr, UInt(trackerId)) + val outer_write_acq = Bundle(Acquire(co.getUncachedWriteAcquireType, + xact.addr, UInt(trackerId), xact.data), + { case TLId => outerId }) + val outer_write_rel = Bundle(Acquire(co.getUncachedWriteAcquireType, + xact.addr, UInt(trackerId), c_rel.payload.data), + { case TLId => outerId }) + val outer_read = Bundle(Acquire(co.getUncachedReadAcquireType, xact.addr, UInt(trackerId)), + { case TLId => outerId }) val probe_initial_flags = Bits(width = nClients) probe_initial_flags := Bits(0) diff --git a/uncore/src/main/scala/tilelink.scala b/uncore/src/main/scala/tilelink.scala index af736c97..8bb98f0a 100644 --- a/uncore/src/main/scala/tilelink.scala +++ b/uncore/src/main/scala/tilelink.scala @@ -3,6 +3,7 @@ package uncore import Chisel._ +case object TLId extends Field[String] case object TLCoherence extends Field[CoherencePolicyWithUncached] case object TLAddrBits extends Field[Int] case object TLMasterXactIdBits extends Field[Int] @@ -155,13 +156,13 @@ class Grant extends MasterSourcedMessage class Finish extends ClientSourcedMessage with HasMasterTransactionId -class UncachedTileLinkIO extends Bundle { +class UncachedTileLinkIO(p: Option[Parameters] = None) extends Bundle()(p) { val acquire = new DecoupledIO(new LogicalNetworkIO(new Acquire)) val grant = new DecoupledIO(new LogicalNetworkIO(new Grant)).flip val finish = new DecoupledIO(new LogicalNetworkIO(new Finish)) } -class TileLinkIO extends UncachedTileLinkIO { +class TileLinkIO(p: Option[Parameters] = None) extends UncachedTileLinkIO(p) { val probe = new DecoupledIO(new LogicalNetworkIO(new Probe)).flip val release = new DecoupledIO(new LogicalNetworkIO(new Release)) } diff --git a/uncore/src/main/scala/uncore.scala b/uncore/src/main/scala/uncore.scala index 2e62d79f..37e535f8 100644 --- a/uncore/src/main/scala/uncore.scala +++ b/uncore/src/main/scala/uncore.scala @@ -15,22 +15,23 @@ abstract trait CoherenceAgentParameters extends UsesParameters { val nClients = params(NClients) } -abstract class CoherenceAgent extends Module +abstract class CoherenceAgent(innerId: String, outerId: String) extends Module with CoherenceAgentParameters { val io = new Bundle { - val inner = (new TileLinkIO).flip - val outer = new UncachedTileLinkIO + val inner = Bundle(new TileLinkIO, {case TLId => innerId}).flip + val outer = Bundle(new UncachedTileLinkIO, {case TLId => outerId}) val incoherent = Vec.fill(nClients){Bool()}.asInput } } -class L2CoherenceAgent(bankId: Int) extends CoherenceAgent { +class L2CoherenceAgent(bankId: Int, innerId: String, outerId: String) extends + CoherenceAgent(innerId, outerId) { // Create SHRs for outstanding transactions val trackerList = (0 until nReleaseTransactors).map(id => - Module(new VoluntaryReleaseTracker(id, bankId))) ++ + Module(new VoluntaryReleaseTracker(id, bankId, innerId, outerId))) ++ (nReleaseTransactors until nTransactors).map(id => - Module(new AcquireTracker(id, bankId))) + Module(new AcquireTracker(id, bankId, innerId, outerId))) // Propagate incoherence flags trackerList.map(_.io.tile_incoherent := io.incoherent.toBits) @@ -82,17 +83,18 @@ class L2CoherenceAgent(bankId: Int) extends CoherenceAgent { ack.ready := Bool(true) // Create an arbiter for the one memory port - val outer_arb = Module(new UncachedTileLinkIOArbiterThatPassesId(trackerList.size)) + val outer_arb = Module(new UncachedTileLinkIOArbiterThatPassesId(trackerList.size), + {case TLId => outerId}) outer_arb.io.in zip trackerList map { case(arb, t) => arb <> t.io.outer } io.outer <> outer_arb.io.out } -abstract class XactTracker extends Module { +abstract class XactTracker(innerId: String, outerId: String) extends Module { val (co, nClients) = (params(TLCoherence),params(NClients)) val io = new Bundle { - val inner = (new TileLinkIO).flip - val outer = new UncachedTileLinkIO + val inner = Bundle(new TileLinkIO, {case TLId => innerId}).flip + val outer = Bundle(new UncachedTileLinkIO, {case TLId => outerId}) val tile_incoherent = Bits(INPUT, params(NClients)) val has_acquire_conflict = Bool(OUTPUT) val has_release_conflict = Bool(OUTPUT) @@ -105,7 +107,7 @@ abstract class XactTracker extends Module { val m_gnt = io.outer.grant.bits } -class VoluntaryReleaseTracker(trackerId: Int, bankId: Int) extends XactTracker { +class VoluntaryReleaseTracker(trackerId: Int, bankId: Int, innerId: String, outerId: String) extends XactTracker(innerId, outerId) { val s_idle :: s_mem :: s_ack :: s_busy :: Nil = Enum(UInt(), 4) val state = Reg(init=s_idle) val xact = Reg{ new Release } @@ -120,10 +122,11 @@ class VoluntaryReleaseTracker(trackerId: Int, bankId: Int) extends XactTracker { io.outer.acquire.valid := Bool(false) io.outer.acquire.bits.header.src := UInt(bankId) //io.outer.acquire.bits.header.dst TODO - io.outer.acquire.bits.payload := Acquire(co.getUncachedWriteAcquireType, + io.outer.acquire.bits.payload := Bundle(Acquire(co.getUncachedWriteAcquireType, xact.addr, UInt(trackerId), - xact.data) + xact.data), + { case TLId => outerId }) io.inner.acquire.ready := Bool(false) io.inner.probe.valid := Bool(false) io.inner.release.ready := Bool(false) @@ -154,7 +157,7 @@ class VoluntaryReleaseTracker(trackerId: Int, bankId: Int) extends XactTracker { } } -class AcquireTracker(trackerId: Int, bankId: Int) extends XactTracker { +class AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: String) extends XactTracker(innerId, outerId) { val s_idle :: s_probe :: s_mem_read :: s_mem_write :: s_make_grant :: s_busy :: Nil = Enum(UInt(), 6) val state = Reg(init=s_idle) val xact = Reg{ new Acquire } @@ -167,11 +170,14 @@ class AcquireTracker(trackerId: Int, bankId: Int) extends XactTracker { val pending_outer_write = co.messageHasData(xact) val pending_outer_read = co.requiresOuterRead(xact.a_type) - val outer_write_acq = Acquire(co.getUncachedWriteAcquireType, - xact.addr, UInt(trackerId), xact.data) - val outer_write_rel = Acquire(co.getUncachedWriteAcquireType, - xact.addr, UInt(trackerId), c_rel.payload.data) - val outer_read = Acquire(co.getUncachedReadAcquireType, xact.addr, UInt(trackerId)) + val outer_write_acq = Bundle(Acquire(co.getUncachedWriteAcquireType, + xact.addr, UInt(trackerId), xact.data), + { case TLId => outerId }) + val outer_write_rel = Bundle(Acquire(co.getUncachedWriteAcquireType, + xact.addr, UInt(trackerId), c_rel.payload.data), + { case TLId => outerId }) + val outer_read = Bundle(Acquire(co.getUncachedReadAcquireType, xact.addr, UInt(trackerId)), + { case TLId => outerId }) val probe_initial_flags = Bits(width = nClients) probe_initial_flags := Bits(0)