From cbe7c51b50112aaa57da9f4e3c41023cf3437968 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 17 Aug 2017 21:27:08 -0700 Subject: [PATCH 1/2] Respect ISA requirements on interrupt priority order https://github.com/riscv/riscv-isa-manual/commit/a62e76cb16eb508199f74632eb8bf263739f25a3 --- src/main/scala/rocket/CSR.scala | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala index 08177c3e..202c8344 100644 --- a/src/main/scala/rocket/CSR.scala +++ b/src/main/scala/rocket/CSR.scala @@ -756,12 +756,15 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param } } - def chooseInterrupt(masks: Seq[UInt]) = { - // we can't simply choose the highest-numbered interrupt, because timer - // interrupts are in the wrong place in mip. - val timerMask = UInt(0xF0, xLen) - val masked = masks.map(m => Cat(m.padTo(xLen) & ~timerMask, m.padTo(xLen) & timerMask)) - (masks.map(_.orR).reduce(_||_), Log2(masked.asUInt)(log2Ceil(xLen)-1, 0)) + def chooseInterrupt(masks: Seq[UInt]): (Bool, UInt) = { + val nonstandard = supported_interrupts.getWidth-1 to 12 by -1 + // MEI, MSI, MTI, SEI, SSI, STI, UEI, USI, UTI + val standard = Seq(11, 3, 7, 9, 1, 5, 8, 0, 4) + val priority = nonstandard ++ standard + val paddedMasks = masks.reverse.map(_.padTo(xLen)) + val any = paddedMasks.flatMap(m => priority.map(i => m(i))).reduce(_||_) + val which = PriorityMux(paddedMasks.flatMap(m => priority.map(i => (m(i), i.U)))) + (any, which) } def readModifyWriteCSR(cmd: UInt, rdata: UInt, wdata: UInt) = From 8087a205ccd7994cc2d9e4c562cc5417ea520f3b Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 17 Aug 2017 22:23:42 -0700 Subject: [PATCH 2/2] Remove redundant check in interrupt priority encoding chooseInterrupts already sorts M interrupts above S interrupts. --- src/main/scala/rocket/CSR.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala index 202c8344..929ce31a 100644 --- a/src/main/scala/rocket/CSR.scala +++ b/src/main/scala/rocket/CSR.scala @@ -300,7 +300,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param val pending_interrupts = read_mip & reg_mie val d_interrupts = reg_debugint << CSR.debugIntCause val m_interrupts = Mux(reg_mstatus.prv <= PRV.S || (reg_mstatus.prv === PRV.M && reg_mstatus.mie), pending_interrupts & ~reg_mideleg, UInt(0)) - val s_interrupts = Mux(m_interrupts === 0 && (reg_mstatus.prv < PRV.S || (reg_mstatus.prv === PRV.S && reg_mstatus.sie)), pending_interrupts & reg_mideleg, UInt(0)) + val s_interrupts = Mux(reg_mstatus.prv < PRV.S || (reg_mstatus.prv === PRV.S && reg_mstatus.sie), pending_interrupts & reg_mideleg, UInt(0)) val (anyInterrupt, whichInterrupt) = chooseInterrupt(Seq(s_interrupts, m_interrupts, d_interrupts)) val interruptMSB = BigInt(1) << (xLen-1) val interruptCause = UInt(interruptMSB) + whichInterrupt