diff --git a/rocket/src/main/scala/cpu.scala b/rocket/src/main/scala/cpu.scala index b87e7549..96b33035 100644 --- a/rocket/src/main/scala/cpu.scala +++ b/rocket/src/main/scala/cpu.scala @@ -161,7 +161,8 @@ class rocketProc extends Component ctrl.io.vec_iface.vcmdq_ready := vu.io.vec_cmdq.ready ctrl.io.vec_iface.vximm1q_ready := vu.io.vec_ximm1q.ready ctrl.io.vec_iface.vximm2q_ready := vu.io.vec_ximm2q.ready - vu.io.vec_ackq.ready := Bool(true) + ctrl.io.vec_iface.vackq_valid := vu.io.vec_ackq.valid + vu.io.vec_ackq.ready := ctrl.io.vec_iface.vackq_ready // hooking up vector memory interface ctrl.io.ext_mem.req_val := vu.io.dmem_req.valid diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index e593dac7..3723ca36 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -580,7 +580,18 @@ class rocketCtrl extends Component val vec = new rocketCtrlVec() io.vec_dpath <> vec.io.dpath - io.vec_iface <> vec.io.iface + + io.vec_iface.vcmdq_valid := vec.io.iface.vcmdq_valid + io.vec_iface.vximm1q_valid := vec.io.iface.vximm1q_valid + io.vec_iface.vximm2q_valid := vec.io.iface.vximm2q_valid + vec.io.iface.vcmdq_ready := io.vec_iface.vcmdq_ready + vec.io.iface.vximm1q_ready := io.vec_iface.vximm1q_ready + vec.io.iface.vximm2q_ready := io.vec_iface.vximm2q_ready + + // FIXME + // use io.vec_iface.vackq_valid + io.vec_iface.vackq_ready := Bool(true) + vec_replay = vec.io.replay vec.io.sr_ev := io.dpath.status(SR_EV) diff --git a/rocket/src/main/scala/ctrl_vec.scala b/rocket/src/main/scala/ctrl_vec.scala index 2c2897d8..1d63cec0 100644 --- a/rocket/src/main/scala/ctrl_vec.scala +++ b/rocket/src/main/scala/ctrl_vec.scala @@ -24,6 +24,8 @@ class ioCtrlVecInterface extends Bundle val vximm1q_ready = Bool(INPUT) val vximm2q_valid = Bool(OUTPUT) val vximm2q_ready = Bool(INPUT) + val vackq_valid = Bool(INPUT) + val vackq_ready = Bool(OUTPUT) } class ioCtrlVec extends Bundle