From 82c595d11aa63f98528caef32d42b5fd4a026a9b Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 10 Mar 2016 17:30:56 -0800 Subject: [PATCH] Fix no-FPU elaboration of CSR file --- rocket/src/main/scala/csr.scala | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala index eb99d7be..9507f6d5 100644 --- a/rocket/src/main/scala/csr.scala +++ b/rocket/src/main/scala/csr.scala @@ -293,7 +293,9 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p) val decoded_addr = read_mapping map { case (k, v) => k -> (addr === k) } val addr_valid = decoded_addr.values.reduce(_||_) - val fp_csr = decoded_addr(CSRs.fflags) || decoded_addr(CSRs.frm) || decoded_addr(CSRs.fcsr) + val fp_csr = + if (usingFPU) decoded_addr(CSRs.fflags) || decoded_addr(CSRs.frm) || decoded_addr(CSRs.fcsr) + else Bool(false) val csr_addr_priv = io.rw.addr(9,8) val priv_sufficient = reg_mstatus.prv >= csr_addr_priv val read_only = io.rw.addr(11,10).andR @@ -442,9 +444,6 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p) reg_mip.msip := wdata(0) } when (decoded_addr(CSRs.mie)) { reg_mie := wdata & supported_interrupts } - when (decoded_addr(CSRs.fflags)) { reg_fflags := wdata } - when (decoded_addr(CSRs.frm)) { reg_frm := wdata } - when (decoded_addr(CSRs.fcsr)) { reg_fflags := wdata; reg_frm := wdata >> reg_fflags.getWidth } when (decoded_addr(CSRs.mepc)) { reg_mepc := ~(~wdata | (coreInstBytes-1)) } when (decoded_addr(CSRs.mscratch)) { reg_mscratch := wdata } if (p(MtvecWritable)) @@ -456,6 +455,11 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p) when (decoded_addr(CSRs.mfromhost)){ when (reg_fromhost === UInt(0) || !host_csr_req_fire) { reg_fromhost := wdata } } when (decoded_addr(CSRs.mtohost)) { when (reg_tohost === UInt(0) || host_csr_req_fire) { reg_tohost := wdata } } when (decoded_addr(CSRs.stats)) { reg_stats := wdata(0) } + if (usingFPU) { + when (decoded_addr(CSRs.fflags)) { reg_fflags := wdata } + when (decoded_addr(CSRs.frm)) { reg_frm := wdata } + when (decoded_addr(CSRs.fcsr)) { reg_fflags := wdata; reg_frm := wdata >> reg_fflags.getWidth } + } if (usingVM) { when (decoded_addr(CSRs.sstatus)) { val new_sstatus = new MStatus().fromBits(wdata)