riscv/rocket-chip
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reset_catch: Allow Test Mode Overrides

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This commit is contained in:
Megan Wachs 2017-09-12 16:05:13 -07:00
parent 063ca0ed4a
commit 82c00cb656
3 changed files with 30 additions and 10 deletions
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7
src/main/scala/devices/debug/Debug.scala
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@ -1029,12 +1029,12 @@ class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int)(implici
val innerCtrl = new AsyncBundle(1, new DebugInternalBundle()).flip
// This comes from tlClk domain.
val debugUnavail = Vec(getNComponents(), Bool()).asInput
val psd = new PSDTestModeIO()
}
dmInner.module.io.innerCtrl := FromAsyncBundle(io.innerCtrl)
dmInner.module.io.dmactive := ~ResetCatchAndSync(clock, ~io.dmactive)
dmInner.module.io.dmactive := ~ResetCatchAndSync(clock, ~io.dmactive, 3, Some("dmactiveSync"), io.psd.test_mode, io.psd.test_mode_reset)
dmInner.module.io.debugUnavail := io.debugUnavail
}
}
@ -1067,6 +1067,7 @@ class TLDebugModule(implicit p: Parameters) extends LazyModule {
val dmi = new ClockedDMIIO().flip
val in = node.bundleIn
val debugInterrupts = intnode.bundleOut
val psd = new PSDTestModeIO()
}
dmOuter.module.io.dmi <> io.dmi.dmi
@ -1077,6 +1078,8 @@ class TLDebugModule(implicit p: Parameters) extends LazyModule {
dmInner.module.io.dmactive := dmOuter.module.io.ctrl.dmactive
dmInner.module.io.debugUnavail := io.ctrl.debugUnavail
io.psd <> dmInner.module.io.psd
io.ctrl <> dmOuter.module.io.ctrl
}

16
src/main/scala/devices/debug/Periphery.scala
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@ -3,7 +3,7 @@
package freechips.rocketchip.devices.debug
import Chisel._
import chisel3.core.{IntParam}
import chisel3.core.{IntParam, Input, Output}
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.coreplex.HasPeripheryBus
import freechips.rocketchip.devices.tilelink._
@ -12,10 +12,10 @@ import freechips.rocketchip.jtag._
import freechips.rocketchip.util._
/** A knob selecting one of the two possible debug interfaces */
case object IncludeJtagDTM extends Field[Boolean]
case object IncludeJtagDTM extends Field[Boolean](false)
/** A wrapper bundle containing one of the two possible debug interfaces */
class DebugIO(implicit p: Parameters) extends ParameterizedBundle()(p) {
class DebugIO(implicit val p: Parameters) extends ParameterizedBundle()(p) with CanHavePSDTestModeIO {
val clockeddmi = (!p(IncludeJtagDTM)).option(new ClockedDMIIO().flip)
val systemjtag = (p(IncludeJtagDTM)).option(new SystemJTAGIO)
val ndreset = Bool(OUTPUT)
@ -48,7 +48,6 @@ trait HasPeripheryDebugBundle {
}
}
}
trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryDebugBundle {
val outer: HasPeripheryDebug
@ -57,6 +56,9 @@ trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryD
debug.clockeddmi.foreach { dbg => outer.debug.module.io.dmi <> dbg }
val dtm = debug.systemjtag.map { sj =>
val psd = debug.psd.getOrElse(Wire(init = new PSDTestModeIO().fromBits(0.U)))
val dtm = Module(new DebugTransportModuleJTAG(p(DebugModuleParams).nDMIAddrSize, p(JtagDTMKey)))
dtm.io.jtag <> sj.jtag
@ -67,7 +69,9 @@ trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryD
outer.debug.module.io.dmi.dmi <> dtm.io.dmi
outer.debug.module.io.dmi.dmiClock := sj.jtag.TCK
outer.debug.module.io.dmi.dmiReset := ResetCatchAndSync(sj.jtag.TCK, sj.reset, "dmiResetCatch")
outer.debug.module.io.psd <> psd
outer.debug.module.io.dmi.dmiReset := ResetCatchAndSync(sj.jtag.TCK, sj.reset, "dmiResetCatch", psd.test_mode, psd.test_mode_reset)
dtm
}

17
src/main/scala/util/ResetCatchAndSync.scala
View File

@ -11,22 +11,30 @@ import Chisel._
class ResetCatchAndSync (sync: Int = 3) extends Module {
override def desiredName = s"ResetCatchAndSync_d${sync}"
val io = new Bundle {
val sync_reset = Bool(OUTPUT)
val psd_test_reset = Bool(INPUT)
val psd_test_mode = Bool(INPUT)
}
io.sync_reset := ~AsyncResetSynchronizerShiftReg(Bool(true), sync)
io.sync_reset := Mux(io.psd_test_mode, io.psd_test_reset,
~AsyncResetSynchronizerShiftReg(Bool(true), sync))
}
object ResetCatchAndSync {
def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None): Bool = {
def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None,
psd_test_mode: Bool = Bool(false), psd_test_reset: Bool = Bool(false)): Bool = {
val catcher = Module (new ResetCatchAndSync(sync))
if (name.isDefined) {catcher.suggestName(name.get)}
catcher.clock := clk
catcher.reset := rst
catcher.io.psd_test_mode := psd_test_mode
catcher.io.psd_test_reset:= psd_test_reset
catcher.io.sync_reset
}
@ -34,4 +42,9 @@ object ResetCatchAndSync {
def apply(clk: Clock, rst: Bool, sync: Int, name: String): Bool = apply(clk, rst, sync, Some(name))
def apply(clk: Clock, rst: Bool, name: String): Bool = apply(clk, rst, name = Some(name))
def apply(clk: Clock, rst: Bool, sync: Int, name: String, psd_test_mode: Bool, psd_test_reset: Bool): Bool = apply(clk, rst, sync, Some(name),
psd_test_mode, psd_test_reset)
def apply(clk: Clock, rst: Bool, name: String, psd_test_mode: Bool, psd_test_reset: Bool): Bool = apply(clk, rst, name = Some(name),
psd_test_mode = psd_test_mode, psd_test_reset = psd_test_reset)
}