riscv/rocket-chip
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reset_catch: Allow Test Mode Overrides

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This commit is contained in:
Megan Wachs
2017-09-12 16:05:13 -07:00
parent 063ca0ed4a
commit 82c00cb656
3 changed files with 30 additions and 10 deletions
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7
src/main/scala/devices/debug/Debug.scala
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@ -1029,12 +1029,12 @@ class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int)(implici
val innerCtrl = new AsyncBundle(1, new DebugInternalBundle()).flip
// This comes from tlClk domain.
val debugUnavail = Vec(getNComponents(), Bool()).asInput
val psd = new PSDTestModeIO()
}
dmInner.module.io.innerCtrl := FromAsyncBundle(io.innerCtrl)
dmInner.module.io.dmactive := ~ResetCatchAndSync(clock, ~io.dmactive)
dmInner.module.io.dmactive := ~ResetCatchAndSync(clock, ~io.dmactive, 3, Some("dmactiveSync"), io.psd.test_mode, io.psd.test_mode_reset)
dmInner.module.io.debugUnavail := io.debugUnavail
}
}
@ -1067,6 +1067,7 @@ class TLDebugModule(implicit p: Parameters) extends LazyModule {
val dmi = new ClockedDMIIO().flip
val in = node.bundleIn
val debugInterrupts = intnode.bundleOut
val psd = new PSDTestModeIO()
}
dmOuter.module.io.dmi <> io.dmi.dmi
@ -1077,6 +1078,8 @@ class TLDebugModule(implicit p: Parameters) extends LazyModule {
dmInner.module.io.dmactive := dmOuter.module.io.ctrl.dmactive
dmInner.module.io.debugUnavail := io.ctrl.debugUnavail
io.psd <> dmInner.module.io.psd
io.ctrl <> dmOuter.module.io.ctrl
}