rocketchip: move TL2 and cake pattern into Coreplex
This commit is contained in:
Wesley W. Terpstra
parent
89139a9492
commit
825c253a72
@ -35,59 +35,53 @@ trait HasCoreplexParameters {
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lazy val outerMemParams = p.alterPartial({ case TLId => "L2toMC" })
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lazy val outerMMIOParams = p.alterPartial({ case TLId => "L2toMMIO" })
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lazy val globalAddrMap = p(rocketchip.GlobalAddrMap)
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lazy val nTiles = p(uncore.devices.NTiles)
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lazy val nExtInterrupts = p(rocketchip.NExtInterrupts)
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lazy val nSlaves = p(rocketchip.NCoreplexExtClients)
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lazy val nMemChannels = p(NMemoryChannels)
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lazy val hasSupervisor = p(rocket.UseVM)
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lazy val nInterruptPriorities = if (nExtInterrupts <= 1) 0 else (nExtInterrupts min 7)
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lazy val plicKey = PLICConfig(nTiles, hasSupervisor, nExtInterrupts, nInterruptPriorities)
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lazy val clintKey = CoreplexLocalInterrupterConfig()
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}
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case class CoreplexConfig(
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nTiles: Int,
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nExtInterrupts: Int,
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nSlaves: Int,
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nMemChannels: Int,
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hasSupervisor: Boolean)
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{
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val nInterruptPriorities = if (nExtInterrupts <= 1) 0 else (nExtInterrupts min 7)
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val plicKey = PLICConfig(nTiles, hasSupervisor, nExtInterrupts, nInterruptPriorities)
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}
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case class CoreplexParameters(implicit val p: Parameters) extends HasCoreplexParameters
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abstract class BaseCoreplex(c: CoreplexConfig)(implicit val p: Parameters) extends LazyModule with HasCoreplexParameters {
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abstract class BareCoreplex(implicit val p: Parameters) extends LazyModule with HasCoreplexParameters {
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val l1tol2 = LazyModule(new TLXbar)
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val mmio = TLOutputNode()
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val lazyTiles = p(BuildTiles) map { _(p) }
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val legacy = LazyModule(new TLLegacy()(outerMMIOParams))
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val debugLegacy = LazyModule(new TLLegacy()(outerMMIOParams))
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val debug = LazyModule(new TLDebugModule())
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debug.node :=
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TLHintHandler()(
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mmio :=
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TLBuffer()(
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TLFragmenter(p(XLen)/8, debugLegacy.tlDataBeats * debugLegacy.tlDataBytes)(
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TLWidthWidget(debugLegacy.tlDataBytes)(debugLegacy.node))))
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val plicLegacy = LazyModule(new TLLegacy()(outerMMIOParams))
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val plic = LazyModule(new TLPLIC(c.plicKey))
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plic.node :=
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TLHintHandler()(
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TLBuffer()(
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TLFragmenter(p(XLen)/8, plicLegacy.tlDataBeats * plicLegacy.tlDataBytes)(
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TLWidthWidget(plicLegacy.tlDataBytes)(plicLegacy.node))))
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TLWidthWidget(legacy.tlDataBytes)(
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l1tol2.node))
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// Kill this once we move TL2 into rocket
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l1tol2.node :=
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TLHintHandler()(
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legacy.node)
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}
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abstract class BaseCoreplexBundle(val c: CoreplexConfig)(implicit val p: Parameters) extends Bundle with HasCoreplexParameters {
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abstract class BareCoreplexBundle[+L <: BareCoreplex](val outer: L) extends Bundle with HasCoreplexParameters {
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implicit val p = outer.p
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val master = new Bundle {
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val mem = Vec(c.nMemChannels, new ClientUncachedTileLinkIO()(outerMemParams))
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val mmio = new ClientUncachedTileLinkIO()(outerMMIOParams)
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val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outerMemParams))
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val mmio = outer.mmio.bundleOut
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}
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val slave = Vec(c.nSlaves, new ClientUncachedTileLinkIO()(innerParams)).flip
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val interrupts = Vec(c.nExtInterrupts, Bool()).asInput
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val debug = new DebugBusIO()(p).flip
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val clint = Vec(c.nTiles, new CoreplexLocalInterrupts).asInput
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val slave = Vec(nSlaves, new ClientUncachedTileLinkIO()(innerParams)).flip
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val resetVector = UInt(INPUT, p(XLen))
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val success = Bool(OUTPUT) // used for testing
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override def cloneType = this.getClass.getConstructors.head.newInstance(c, p).asInstanceOf[this.type]
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override def cloneType = this.getClass.getConstructors.head.newInstance(outer).asInstanceOf[this.type]
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}
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abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
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c: CoreplexConfig, l: L, b: B)(implicit val p: Parameters) extends LazyModuleImp(l) with HasCoreplexParameters {
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val outer: L = l
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val io: B = b
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abstract class BareCoreplexModule[+L <: BareCoreplex, +B <: BareCoreplexBundle[L]](val outer: L, val io: B) extends LazyModuleImp(outer) with HasCoreplexParameters {
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implicit val p = outer.p
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// Build a set of Tiles
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val tiles = outer.lazyTiles.map(_.module)
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@ -95,9 +89,8 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
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val nCachedPorts = tiles.map(tile => tile.io.cached.size).reduce(_ + _)
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val nUncachedPorts = tiles.map(tile => tile.io.uncached.size).reduce(_ + _)
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val nBanks = c.nMemChannels * nBanksPerMemChannel
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// Build an uncore backing the Tiles
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val nBanks = nMemChannels * nBanksPerMemChannel
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buildUncore(p.alterPartial({
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case HastiId => "TL"
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case TLId => "L1toL2"
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@ -105,7 +98,7 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
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case NUncachedTileLinkPorts => nUncachedPorts
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}))
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def buildUncore(implicit p: Parameters) = {
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def buildUncore(implicit p: Parameters) {
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// Create a simple L1toL2 NoC between the tiles and the banks of outer memory
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// Cached ports are first in client list, making sharerToClientId just an indentity function
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// addrToBank is sed to hash physical addresses (of cache blocks) to banks (and thereby memory channels)
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@ -130,9 +123,10 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
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// and coherence manager(s) to the other side
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l1tol2net.io.clients_cached <> uncoreTileIOs.map(_.cached).flatten
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l1tol2net.io.clients_uncached <> uncoreTileIOs.map(_.uncached).flatten ++ io.slave
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l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner // legacy goes here (not mmioManager)
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l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner
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outer.legacy.module.io.legacy <> mmioManager.io.outer
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val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, c.nMemChannels)(outerMemParams))
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val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, nMemChannels)(outerMemParams))
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val backendBuffering = TileLinkDepths(0,0,0,0,0)
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for ((bank, icPort) <- managerEndpoints zip mem_ic.io.in) {
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@ -141,43 +135,80 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
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}
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io.master.mem <> mem_ic.io.out
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buildMMIONetwork(TileLinkEnqueuer(mmioManager.io.outer, 1))(outerMMIOParams)
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}
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def buildMMIONetwork(mmio: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
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val ioAddrMap = globalAddrMap.subMap("io")
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val cBus = Module(new TileLinkRecursiveInterconnect(1, ioAddrMap))
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cBus.io.in.head <> mmio
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outer.plicLegacy.module.io.legacy <> cBus.port("cbus:plic")
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for (i <- 0 until io.interrupts.size) {
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val gateway = Module(new LevelGateway)
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gateway.io.interrupt := io.interrupts(i)
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outer.plic.module.io.devices(i) <> gateway.io.plic
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}
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outer.debugLegacy.module.io.legacy <> cBus.port("cbus:debug")
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outer.debug.module.io.db <> io.debug
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// connect coreplex-internal interrupts to tiles
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for ((tile, i) <- (uncoreTileIOs zipWithIndex)) {
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tile.interrupts <> io.clint(i)
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tile.interrupts.meip := outer.plic.module.io.harts(c.plicKey.context(i, 'M'))
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tile.interrupts.seip.foreach(_ := outer.plic.module.io.harts(c.plicKey.context(i, 'S')))
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tile.interrupts.debug := outer.debug.module.io.debugInterrupts(i)
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tile.hartid := UInt(i)
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tile.resetVector := io.resetVector
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}
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val tileSlavePorts = (0 until c.nTiles) map (i => s"cbus:dmem$i") filter (ioAddrMap contains _)
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for ((t, m) <- (uncoreTileIOs.map(_.slave).flatten) zip (tileSlavePorts map (cBus port _)))
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t <> m
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io.master.mmio <> cBus.port("TL2")
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for ((tile, i) <- (uncoreTileIOs zipWithIndex)) {
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tile.hartid := UInt(i)
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tile.resetVector := io.resetVector
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}
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// Coreplex doesn't know when to stop running
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io.success := Bool(false)
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}
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trait CoreplexPeripherals extends HasCoreplexParameters {
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val module: CoreplexPeripheralsModule
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val l1tol2: TLXbar
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val legacy: TLLegacy
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val lazyTiles: Seq[LazyTile]
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val cbus = LazyModule(new TLXbar)
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val debug = LazyModule(new TLDebugModule())
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val plic = LazyModule(new TLPLIC(() => plicKey))
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val clint = LazyModule(new CoreplexLocalInterrupter(clintKey))
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cbus.node :=
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TLAtomicAutomata(arithmetic = true)( // disable once TLB uses TL2 metadata
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TLWidthWidget(legacy.tlDataBytes)(
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TLBuffer()(
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l1tol2.node)))
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debug.node := TLFragmenter(p(XLen)/8, legacy.tlDataBeats * legacy.tlDataBytes)(cbus.node)
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plic.node := TLFragmenter(p(XLen)/8, legacy.tlDataBeats * legacy.tlDataBytes)(cbus.node)
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clint.node := TLFragmenter(p(XLen)/8, legacy.tlDataBeats * legacy.tlDataBytes)(cbus.node)
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lazyTiles.map(_.slave).flatten.foreach { scratch =>
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scratch := TLFragmenter(p(XLen)/8, legacy.tlDataBeats * legacy.tlDataBytes)(cbus.node)
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}
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}
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trait CoreplexPeripheralsBundle extends HasCoreplexParameters {
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val outer: CoreplexPeripherals
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val debug = new DebugBusIO().flip
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val interrupts = Vec(nExtInterrupts, Bool()).asInput
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}
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trait CoreplexPeripheralsModule extends HasCoreplexParameters {
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val outer: CoreplexPeripherals
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val io: CoreplexPeripheralsBundle
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val uncoreTileIOs: Seq[TileIO]
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for (i <- 0 until io.interrupts.size) {
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val gateway = Module(new LevelGateway)
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gateway.io.interrupt := io.interrupts(i)
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outer.plic.module.io.devices(i) <> gateway.io.plic
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}
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outer.debug.module.io.db <> io.debug
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outer.clint.module.io.rtcTick := Counter(p(rocketchip.RTCPeriod)).inc()
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// connect coreplex-internal interrupts to tiles
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for ((tile, i) <- (uncoreTileIOs zipWithIndex)) {
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tile.interrupts <> outer.clint.module.io.tiles(i)
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tile.interrupts.meip := outer.plic.module.io.harts(plicKey.context(i, 'M'))
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tile.interrupts.seip.foreach(_ := outer.plic.module.io.harts(plicKey.context(i, 'S')))
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tile.interrupts.debug := outer.debug.module.io.debugInterrupts(i)
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}
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}
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class BaseCoreplex(implicit p: Parameters) extends BareCoreplex
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with CoreplexPeripherals {
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override lazy val module = new BaseCoreplexModule(this, new BaseCoreplexBundle(this))
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}
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class BaseCoreplexBundle[+L <: BaseCoreplex](outer: L) extends BareCoreplexBundle(outer)
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with CoreplexPeripheralsBundle
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class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle[L]](outer: L, io: B) extends BareCoreplexModule(outer, io)
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with CoreplexPeripheralsModule
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@ -18,7 +18,7 @@ trait DirectConnection {
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(tiles zip uncoreTileIOs) foreach { case (tile, uncore) =>
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(uncore.cached zip tile.io.cached) foreach { case (u, t) => u <> TileLinkEnqueuer(t, tlBuffering) }
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(uncore.uncached zip tile.io.uncached) foreach { case (u, t) => u <> TileLinkEnqueuer(t, ultBuffering) }
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tile.io.slave.foreach { _ <> TileLinkEnqueuer(uncore.slave.get, 1) }
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// !!! tile.io.slave.foreach { _ <> TileLinkEnqueuer(uncore.slave.get, 1) }
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tile.io.interrupts <> uncore.interrupts
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@ -27,21 +27,19 @@ trait DirectConnection {
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}
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}
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class DefaultCoreplex(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplex(c)(p) {
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override lazy val module = Module(new DefaultCoreplexModule(c, this, new DefaultCoreplexBundle(c)(p))(p))
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class DefaultCoreplex(implicit p: Parameters) extends BaseCoreplex {
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override lazy val module = new DefaultCoreplexModule(this, new DefaultCoreplexBundle(this))
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}
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class DefaultCoreplexBundle(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplexBundle(c)(p)
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class DefaultCoreplexBundle[+L <: DefaultCoreplex](outer: L) extends BaseCoreplexBundle(outer)
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class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle](
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c: CoreplexConfig, l: L, b: B)(implicit p: Parameters) extends BaseCoreplexModule(c, l, b)(p)
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class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle[L]](outer: L, io: B) extends BaseCoreplexModule(outer, io)
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with DirectConnection
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/////
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trait TileClockResetBundle {
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val c: CoreplexConfig
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val tcrs = Vec(c.nTiles, new Bundle {
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trait TileClockResetBundle extends HasCoreplexParameters {
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val tcrs = Vec(nTiles, new Bundle {
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val clock = Clock(INPUT)
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val reset = Bool(INPUT)
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})
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@ -58,7 +56,7 @@ trait AsyncConnection {
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(uncore.cached zip tile.io.cached) foreach { case (u, t) => u <> AsyncTileLinkFrom(tcr.clock, tcr.reset, t) }
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(uncore.uncached zip tile.io.uncached) foreach { case (u, t) => u <> AsyncUTileLinkFrom(tcr.clock, tcr.reset, t) }
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tile.io.slave.foreach { _ <> AsyncUTileLinkTo(tcr.clock, tcr.reset, uncore.slave.get)}
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// !!! tile.io.slave.foreach { _ <> AsyncUTileLinkTo(tcr.clock, tcr.reset, uncore.slave.get)}
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val ti = tile.io.interrupts
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val ui = uncore.interrupts
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@ -73,13 +71,12 @@ trait AsyncConnection {
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}
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}
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class MultiClockCoreplex(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplex(c)(p) {
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override lazy val module = Module(new MultiClockCoreplexModule(c, this, new MultiClockCoreplexBundle(c)(p))(p))
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class MultiClockCoreplex(implicit p: Parameters) extends BaseCoreplex {
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override lazy val module = new MultiClockCoreplexModule(this, new MultiClockCoreplexBundle(this))
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}
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class MultiClockCoreplexBundle(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplexBundle(c)(p)
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class MultiClockCoreplexBundle[+L <: MultiClockCoreplex](outer: L) extends BaseCoreplexBundle(outer)
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with TileClockResetBundle
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class MultiClockCoreplexModule[+L <: MultiClockCoreplex, +B <: MultiClockCoreplexBundle](
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c: CoreplexConfig, l: L, b: B)(implicit p: Parameters) extends BaseCoreplexModule(c, l, b)(p)
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class MultiClockCoreplexModule[+L <: MultiClockCoreplex, +B <: MultiClockCoreplexBundle[L]](outer: L, io: B) extends BaseCoreplexModule(outer, io)
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with AsyncConnection
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@ -72,8 +72,6 @@ class Edge32BitMemtestConfig extends Config(
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/* Composable Configs to set individual parameters */
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class WithGroundTest extends Config(
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(pname, site, here) => pname match {
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case BuildCoreplex =>
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(c: CoreplexConfig, p: Parameters) => LazyModule(new GroundTestCoreplex(c)(p)).module
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case TLKey("L1toL2") => {
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val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
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val dataBeats = (8 * site(CacheBlockBytes)) / site(XLen)
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@ -106,7 +104,7 @@ class WithGroundTest extends Config(
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}
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}
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case BuildExampleTop =>
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(p: Parameters) => LazyModule(new ExampleTopWithTestRAM(p))
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(p: Parameters) => LazyModule(new ExampleTopWithTestRAM(new GroundTestCoreplex()(_))(p))
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case FPUKey => None
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case UseAtomics => false
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case UseCompressed => false
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@ -4,13 +4,13 @@ import Chisel._
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import cde.{Parameters}
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import coreplex._
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class GroundTestCoreplex(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplex(c)(p) {
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override lazy val module = Module(new GroundTestCoreplexModule(c, this, new GroundTestCoreplexBundle(c)(p))(p))
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class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex {
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override lazy val module = new GroundTestCoreplexModule(this, new GroundTestCoreplexBundle(this))
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}
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class GroundTestCoreplexBundle(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplexBundle(c)(p)
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class GroundTestCoreplexBundle[+L <: GroundTestCoreplex](outer: L) extends BaseCoreplexBundle(outer)
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class GroundTestCoreplexModule[+L <: GroundTestCoreplex, +B <: GroundTestCoreplexBundle](
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c: CoreplexConfig, l: L, b: B)(implicit p: Parameters) extends BaseCoreplexModule(c, l, b)(p) with DirectConnection {
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class GroundTestCoreplexModule[+L <: GroundTestCoreplex, +B <: GroundTestCoreplexBundle[L]](outer: L, io: B) extends BaseCoreplexModule(outer, io)
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with DirectConnection {
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io.success := tiles.flatMap(_.io.elements get "success").map(_.asInstanceOf[Bool]).reduce(_&&_)
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}
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@ -97,6 +97,7 @@ abstract class GroundTest(implicit val p: Parameters) extends Module
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}
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class GroundTestTile(implicit val p: Parameters) extends LazyTile with HasGroundTestParameters {
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val slave = None
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lazy val module = new TileImp(this) {
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val io = new TileIO(bc) {
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val success = Bool(OUTPUT)
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@ -497,7 +497,7 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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}
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}
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class ScratchpadSlavePort(implicit p: Parameters) extends LazyModule {
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class ScratchpadSlavePort(implicit val p: Parameters) extends LazyModule with HasCoreParameters {
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val beatBytes = p(XLen)/8
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val node = TLManagerNode(TLManagerPortParameters(
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Seq(TLManagerParameters(
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@ -510,7 +510,7 @@ class ScratchpadSlavePort(implicit p: Parameters) extends LazyModule {
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beatBytes = beatBytes,
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minLatency = 1))
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lazy val module = new LazyModuleImp(this) with HasCoreParameters {
|
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lazy val module = new LazyModuleImp(this) {
|
||||
val io = new Bundle {
|
||||
val tl_in = node.bundleIn
|
||||
val dmem = new HellaCacheIO
|
||||
|
||||
@ -54,6 +54,7 @@ abstract class LazyTile(implicit p: Parameters) extends LazyModule {
|
||||
xLen = p(XLen))
|
||||
|
||||
val module: TileImp
|
||||
val slave: Option[TLOutputNode]
|
||||
}
|
||||
|
||||
class RocketTile(implicit p: Parameters) extends LazyTile {
|
||||
|
||||
@ -17,13 +17,12 @@ import coreplex._
|
||||
case object GlobalAddrMap extends Field[AddrMap]
|
||||
case object ConfigString extends Field[String]
|
||||
case object NCoreplexExtClients extends Field[Int]
|
||||
case object NExtInterrupts extends Field[Int]
|
||||
/** Enable or disable monitoring of Diplomatic buses */
|
||||
case object TLEmitMonitors extends Field[Bool]
|
||||
/** Function for building Coreplex */
|
||||
case object BuildCoreplex extends Field[(CoreplexConfig, Parameters) => BaseCoreplexModule[BaseCoreplex, BaseCoreplexBundle]]
|
||||
|
||||
/** Base Top with no Periphery */
|
||||
abstract class BaseTop(q: Parameters) extends LazyModule {
|
||||
abstract class BaseTop[+C <: BaseCoreplex](buildCoreplex: Parameters => C)(implicit q: Parameters) extends LazyModule {
|
||||
// the following variables will be refactored properly with TL2
|
||||
val pInterrupts = new RangeManager
|
||||
val pBusMasters = new RangeManager
|
||||
@ -35,52 +34,39 @@ abstract class BaseTop(q: Parameters) extends LazyModule {
|
||||
val peripheryBus = LazyModule(new TLXbar)
|
||||
lazy val peripheryManagers = socBus.node.edgesIn(0).manager.managers
|
||||
|
||||
lazy val c = CoreplexConfig(
|
||||
nTiles = q(NTiles),
|
||||
nExtInterrupts = pInterrupts.sum,
|
||||
nSlaves = pBusMasters.sum,
|
||||
nMemChannels = q(NMemoryChannels),
|
||||
hasSupervisor = q(UseVM)
|
||||
)
|
||||
// Fill in the TL1 legacy parameters
|
||||
val qWithSums = q.alterPartial {
|
||||
case NCoreplexExtClients => pBusMasters.sum
|
||||
case NExtInterrupts => pInterrupts.sum
|
||||
}
|
||||
val qWithMap = qWithSums.alterPartial {
|
||||
case GlobalAddrMap => GenerateGlobalAddrMap(qWithSums, peripheryManagers)
|
||||
}
|
||||
implicit val p = qWithMap.alterPartial {
|
||||
case ConfigString => GenerateConfigString(qWithMap, peripheryManagers)
|
||||
}
|
||||
|
||||
lazy val genGlobalAddrMap = GenerateGlobalAddrMap(q, peripheryManagers)
|
||||
private val qWithMap = q.alterPartial({case GlobalAddrMap => genGlobalAddrMap})
|
||||
|
||||
lazy val genConfigString = GenerateConfigString(qWithMap, c, peripheryManagers)
|
||||
implicit val p = qWithMap.alterPartial({
|
||||
case ConfigString => genConfigString
|
||||
case NCoreplexExtClients => pBusMasters.sum})
|
||||
|
||||
val legacy = LazyModule(new TLLegacy()(p.alterPartial({ case TLId => "L2toMMIO" })))
|
||||
val coreplex = LazyModule(buildCoreplex(p))
|
||||
|
||||
peripheryBus.node :=
|
||||
TLWidthWidget(p(SOCBusKey).beatBytes)(
|
||||
TLBuffer()(
|
||||
TLAtomicAutomata(arithmetic = p(PeripheryBusKey).arithAMO)(
|
||||
TLWidthWidget(p(SOCBusKey).beatBytes)(
|
||||
socBus.node)))
|
||||
|
||||
socBus.node :=
|
||||
TLWidthWidget(legacy.tlDataBytes)(
|
||||
TLHintHandler()(
|
||||
legacy.node))
|
||||
socBus.node := coreplex.mmio
|
||||
|
||||
TopModule.contents = Some(this)
|
||||
}
|
||||
|
||||
abstract class BaseTopBundle[+L <: BaseTop](
|
||||
val p: Parameters,
|
||||
val outer: L) extends Bundle {
|
||||
abstract class BaseTopBundle[+L <: BaseTop[BaseCoreplex]](val outer: L) extends Bundle {
|
||||
implicit val p = outer.p
|
||||
val success = Bool(OUTPUT)
|
||||
}
|
||||
|
||||
abstract class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle[L]](
|
||||
val p: Parameters,
|
||||
val outer: L,
|
||||
val io: B) extends LazyModuleImp(outer) {
|
||||
val coreplex = p(BuildCoreplex)(outer.c, p)
|
||||
val coreplexIO = Wire(coreplex.io)
|
||||
|
||||
outer.legacy.module.io.legacy <> coreplexIO.master.mmio
|
||||
abstract class BaseTopModule[+L <: BaseTop[BaseCoreplex], +B <: BaseTopBundle[L]](val outer: L, val io: B) extends LazyModuleImp(outer) {
|
||||
implicit val p = outer.p
|
||||
val coreplexIO = Wire(outer.coreplex.module.io)
|
||||
|
||||
println("Generated Address Map")
|
||||
for (entry <- p(GlobalAddrMap).flatten) {
|
||||
@ -106,8 +92,8 @@ abstract class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle[L]](
|
||||
}
|
||||
|
||||
trait DirectConnection {
|
||||
val coreplexIO: BaseCoreplexBundle
|
||||
val coreplex: BaseCoreplexModule[BaseCoreplex, BaseCoreplexBundle]
|
||||
val coreplexIO: BaseCoreplexBundle[BaseCoreplex]
|
||||
val outer: BaseTop[BaseCoreplex]
|
||||
|
||||
coreplexIO <> coreplex.io
|
||||
coreplexIO <> outer.coreplex.module.io
|
||||
}
|
||||
|
||||
@ -40,8 +40,6 @@ class BasePlatformConfig extends Config(
|
||||
site(TLKey("L2toMC")).copy(dataBeats = edgeDataBeats)
|
||||
case TLKey("MMIOtoEdge") =>
|
||||
site(TLKey("L2toMMIO")).copy(dataBeats = edgeDataBeats)
|
||||
case BuildCoreplex =>
|
||||
(c: CoreplexConfig, p: Parameters) => LazyModule(new DefaultCoreplex(c)(p)).module
|
||||
case NExtTopInterrupts => 2
|
||||
case SOCBusKey => SOCBusConfig(beatBytes = site(TLKey("L2toMMIO")).dataBitsPerBeat/8)
|
||||
case PeripheryBusKey => PeripheryBusConfig(arithAMO = true, beatBytes = 4)
|
||||
@ -65,7 +63,7 @@ class BasePlatformConfig extends Config(
|
||||
case ExtMemSize => Dump("MEM_SIZE", 0x10000000L)
|
||||
case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
|
||||
case BuildExampleTop =>
|
||||
(p: Parameters) => LazyModule(new ExampleTop(p))
|
||||
(p: Parameters) => LazyModule(new ExampleTop(new DefaultCoreplex()(_))(p))
|
||||
case SimMemLatency => 0
|
||||
case _ => throw new CDEMatchError
|
||||
}
|
||||
|
||||
@ -9,17 +9,17 @@ import coreplex._
|
||||
import rocketchip._
|
||||
|
||||
/** Example Top with Periphery */
|
||||
class ExampleTop(q: Parameters) extends BaseTop(q)
|
||||
class ExampleTop[+C <: BaseCoreplex](buildCoreplex: Parameters => C)(implicit p: Parameters) extends BaseTop(buildCoreplex)
|
||||
with PeripheryBootROM
|
||||
with PeripheryDebug
|
||||
with PeripheryExtInterrupts
|
||||
with PeripheryMasterMem
|
||||
with PeripheryMasterAXI4MMIO
|
||||
with PeripherySlave {
|
||||
override lazy val module = Module(new ExampleTopModule(p, this, new ExampleTopBundle(p, this)))
|
||||
override lazy val module = new ExampleTopModule(this, new ExampleTopBundle(this))
|
||||
}
|
||||
|
||||
class ExampleTopBundle[+L <: ExampleTop](p: Parameters, l: L) extends BaseTopBundle(p, l)
|
||||
class ExampleTopBundle[+L <: ExampleTop[BaseCoreplex]](outer: L) extends BaseTopBundle(outer)
|
||||
with PeripheryBootROMBundle
|
||||
with PeripheryDebugBundle
|
||||
with PeripheryExtInterruptsBundle
|
||||
@ -27,7 +27,7 @@ class ExampleTopBundle[+L <: ExampleTop](p: Parameters, l: L) extends BaseTopBun
|
||||
with PeripheryMasterAXI4MMIOBundle
|
||||
with PeripherySlaveBundle
|
||||
|
||||
class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle[L]](p: Parameters, l: L, b: B) extends BaseTopModule(p, l, b)
|
||||
class ExampleTopModule[+L <: ExampleTop[BaseCoreplex], +B <: ExampleTopBundle[L]](outer: L, io: B) extends BaseTopModule(outer, io)
|
||||
with PeripheryBootROMModule
|
||||
with PeripheryDebugModule
|
||||
with PeripheryExtInterruptsModule
|
||||
@ -38,13 +38,13 @@ class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle[L]](p: Parameter
|
||||
with DirectConnection
|
||||
|
||||
/** Example Top with TestRAM */
|
||||
class ExampleTopWithTestRAM(q: Parameters) extends ExampleTop(q)
|
||||
class ExampleTopWithTestRAM[+C <: BaseCoreplex](buildCoreplex: Parameters => C)(implicit p: Parameters) extends ExampleTop(buildCoreplex)
|
||||
with PeripheryTestRAM {
|
||||
override lazy val module = Module(new ExampleTopWithTestRAMModule(p, this, new ExampleTopWithTestRAMBundle(p, this)))
|
||||
override lazy val module = new ExampleTopWithTestRAMModule(this, new ExampleTopWithTestRAMBundle(this))
|
||||
}
|
||||
|
||||
class ExampleTopWithTestRAMBundle[+L <: ExampleTopWithTestRAM](p: Parameters, l: L) extends ExampleTopBundle(p, l)
|
||||
class ExampleTopWithTestRAMBundle[+L <: ExampleTopWithTestRAM[BaseCoreplex]](outer: L) extends ExampleTopBundle(outer)
|
||||
with PeripheryTestRAMBundle
|
||||
|
||||
class ExampleTopWithTestRAMModule[+L <: ExampleTopWithTestRAM, +B <: ExampleTopWithTestRAMBundle[L]](p: Parameters, l: L, b: B) extends ExampleTopModule(p, l, b)
|
||||
class ExampleTopWithTestRAMModule[+L <: ExampleTopWithTestRAM[BaseCoreplex], +B <: ExampleTopWithTestRAMBundle[L]](outer: L, io: B) extends ExampleTopModule(outer, io)
|
||||
with PeripheryTestRAMModule
|
||||
|
||||
@ -110,7 +110,7 @@ trait PeripheryDebugModule {
|
||||
implicit val p: Parameters
|
||||
val outer: PeripheryDebug
|
||||
val io: PeripheryDebugBundle
|
||||
val coreplexIO: BaseCoreplexBundle
|
||||
val coreplexIO: BaseCoreplexBundle[BaseCoreplex]
|
||||
|
||||
if (p(IncludeJtagDTM)) {
|
||||
// JtagDTMWithSync is a wrapper which
|
||||
@ -143,7 +143,7 @@ trait PeripheryExtInterruptsModule {
|
||||
implicit val p: Parameters
|
||||
val outer: PeripheryExtInterrupts
|
||||
val io: PeripheryExtInterruptsBundle
|
||||
val coreplexIO: BaseCoreplexBundle
|
||||
val coreplexIO: BaseCoreplexBundle[BaseCoreplex]
|
||||
|
||||
{
|
||||
val r = outer.pInterrupts.range("ext")
|
||||
@ -172,7 +172,7 @@ trait PeripheryMasterMemModule extends HasPeripheryParameters {
|
||||
implicit val p: Parameters
|
||||
val outer: PeripheryMasterMem
|
||||
val io: PeripheryMasterMemBundle
|
||||
val coreplexIO: BaseCoreplexBundle
|
||||
val coreplexIO: BaseCoreplexBundle[BaseCoreplex]
|
||||
|
||||
val edgeMem = coreplexIO.master.mem.map(TileLinkWidthAdapter(_, edgeMemParams))
|
||||
|
||||
@ -199,8 +199,9 @@ trait PeripheryMasterMemModule extends HasPeripheryParameters {
|
||||
/////
|
||||
|
||||
// PeripheryMasterAXI4MMIO is an example, make your own cake pattern like this one.
|
||||
trait PeripheryMasterAXI4MMIO extends BaseTop with HasPeripheryParameters {
|
||||
trait PeripheryMasterAXI4MMIO extends HasPeripheryParameters {
|
||||
implicit val p: Parameters
|
||||
val socBus: TLXbar
|
||||
|
||||
val mmio_axi4 = AXI4BlindOutputNode(AXI4SlavePortParameters(
|
||||
slaves = Seq(AXI4SlaveParameters(
|
||||
@ -253,7 +254,7 @@ trait PeripherySlaveModule extends HasPeripheryParameters {
|
||||
implicit val p: Parameters
|
||||
val outer: PeripherySlave
|
||||
val io: PeripherySlaveBundle
|
||||
val coreplexIO: BaseCoreplexBundle
|
||||
val coreplexIO: BaseCoreplexBundle[BaseCoreplex]
|
||||
|
||||
if (p(NExtBusAXIChannels) > 0) {
|
||||
val arb = Module(new NastiArbiter(p(NExtBusAXIChannels)))
|
||||
@ -339,6 +340,6 @@ trait PeripheryTestBusMasterModule {
|
||||
/////
|
||||
|
||||
trait HardwiredResetVector {
|
||||
val coreplexIO: BaseCoreplexBundle
|
||||
val coreplexIO: BaseCoreplexBundle[BaseCoreplex]
|
||||
coreplexIO.resetVector := UInt(0x1000) // boot ROM
|
||||
}
|
||||
|
||||
@ -8,14 +8,14 @@ import junctions._
|
||||
import junctions.NastiConstants._
|
||||
import util.LatencyPipe
|
||||
|
||||
case object BuildExampleTop extends Field[Parameters => ExampleTop]
|
||||
case object BuildExampleTop extends Field[Parameters => ExampleTop[coreplex.BaseCoreplex]]
|
||||
case object SimMemLatency extends Field[Int]
|
||||
|
||||
class TestHarness(q: Parameters) extends Module {
|
||||
val io = new Bundle {
|
||||
val success = Bool(OUTPUT)
|
||||
}
|
||||
val dut = q(BuildExampleTop)(q).module
|
||||
val dut = Module(q(BuildExampleTop)(q).module)
|
||||
implicit val p = dut.p
|
||||
|
||||
// This test harness isn't especially flexible yet
|
||||
|
||||
@ -104,7 +104,8 @@ object GenerateGlobalAddrMap {
|
||||
}
|
||||
|
||||
object GenerateConfigString {
|
||||
def apply(p: Parameters, c: CoreplexConfig, peripheryManagers: Seq[TLManagerParameters]) = {
|
||||
def apply(p: Parameters, peripheryManagers: Seq[TLManagerParameters]) = {
|
||||
val c = CoreplexParameters()(p)
|
||||
val addrMap = p(GlobalAddrMap)
|
||||
val plicAddr = addrMap("io:cbus:plic").start
|
||||
val clint = CoreplexLocalInterrupterConfig()
|
||||
|
||||
Loading…
Reference in New Issue
Block a user