rocketchip: move TL2 and cake pattern into Coreplex

src/main/scala/coreplex/BaseCoreplex.scala

@@ -35,59 +35,53 @@ trait HasCoreplexParameters {
   lazy val outerMemParams = p.alterPartial({ case TLId => "L2toMC" })
   lazy val outerMMIOParams = p.alterPartial({ case TLId => "L2toMMIO" })
   lazy val globalAddrMap = p(rocketchip.GlobalAddrMap)
+  lazy val nTiles = p(uncore.devices.NTiles)
+  lazy val nExtInterrupts = p(rocketchip.NExtInterrupts)
+  lazy val nSlaves = p(rocketchip.NCoreplexExtClients)
+  lazy val nMemChannels = p(NMemoryChannels)
+  lazy val hasSupervisor = p(rocket.UseVM)
+
+  lazy val nInterruptPriorities = if (nExtInterrupts <= 1) 0 else (nExtInterrupts min 7)
+  lazy val plicKey = PLICConfig(nTiles, hasSupervisor, nExtInterrupts, nInterruptPriorities)
+  lazy val clintKey = CoreplexLocalInterrupterConfig()
 }
 
-case class CoreplexConfig(
+case class CoreplexParameters(implicit val p: Parameters) extends HasCoreplexParameters
-    nTiles: Int,
-    nExtInterrupts: Int,
-    nSlaves: Int,
-    nMemChannels: Int,
-    hasSupervisor: Boolean)
-{
-  val nInterruptPriorities = if (nExtInterrupts <= 1) 0 else (nExtInterrupts min 7)
-  val plicKey = PLICConfig(nTiles, hasSupervisor, nExtInterrupts, nInterruptPriorities)
-}
 
-abstract class BaseCoreplex(c: CoreplexConfig)(implicit val p: Parameters) extends LazyModule with HasCoreplexParameters {
+abstract class BareCoreplex(implicit val p: Parameters) extends LazyModule with HasCoreplexParameters {
+  val l1tol2 = LazyModule(new TLXbar)
+  val mmio = TLOutputNode()
   val lazyTiles = p(BuildTiles) map { _(p) }
+  val legacy = LazyModule(new TLLegacy()(outerMMIOParams))
 
-  val debugLegacy = LazyModule(new TLLegacy()(outerMMIOParams))
+  mmio :=
-  val debug = LazyModule(new TLDebugModule())
-  debug.node :=
-  TLHintHandler()(
     TLBuffer()(
-      TLFragmenter(p(XLen)/8, debugLegacy.tlDataBeats * debugLegacy.tlDataBytes)(
+    TLWidthWidget(legacy.tlDataBytes)(
-        TLWidthWidget(debugLegacy.tlDataBytes)(debugLegacy.node))))
+    l1tol2.node))
 
-  val plicLegacy = LazyModule(new TLLegacy()(outerMMIOParams))
+  // Kill this once we move TL2 into rocket
-  val plic = LazyModule(new TLPLIC(c.plicKey))
+  l1tol2.node :=
-  plic.node :=
     TLHintHandler()(
-    TLBuffer()(
+    legacy.node)
-      TLFragmenter(p(XLen)/8, plicLegacy.tlDataBeats * plicLegacy.tlDataBytes)(
-        TLWidthWidget(plicLegacy.tlDataBytes)(plicLegacy.node))))
-
 }
 
-abstract class BaseCoreplexBundle(val c: CoreplexConfig)(implicit val p: Parameters) extends Bundle with HasCoreplexParameters {
+abstract class BareCoreplexBundle[+L <: BareCoreplex](val outer: L) extends Bundle with HasCoreplexParameters {
+  implicit val p = outer.p
+
   val master = new Bundle {
-    val mem = Vec(c.nMemChannels, new ClientUncachedTileLinkIO()(outerMemParams))
+    val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outerMemParams))
-    val mmio = new ClientUncachedTileLinkIO()(outerMMIOParams)
+    val mmio = outer.mmio.bundleOut
   }
-  val slave = Vec(c.nSlaves, new ClientUncachedTileLinkIO()(innerParams)).flip
+
-  val interrupts = Vec(c.nExtInterrupts, Bool()).asInput
+  val slave = Vec(nSlaves, new ClientUncachedTileLinkIO()(innerParams)).flip
-  val debug = new DebugBusIO()(p).flip
-  val clint = Vec(c.nTiles, new CoreplexLocalInterrupts).asInput
   val resetVector = UInt(INPUT, p(XLen))
   val success = Bool(OUTPUT) // used for testing
 
-  override def cloneType = this.getClass.getConstructors.head.newInstance(c, p).asInstanceOf[this.type]
+  override def cloneType = this.getClass.getConstructors.head.newInstance(outer).asInstanceOf[this.type]
 }
 
-abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
+abstract class BareCoreplexModule[+L <: BareCoreplex, +B <: BareCoreplexBundle[L]](val outer: L, val io: B) extends LazyModuleImp(outer) with HasCoreplexParameters {
-    c: CoreplexConfig, l: L, b: B)(implicit val p: Parameters) extends LazyModuleImp(l) with HasCoreplexParameters {
+  implicit val p = outer.p
-  val outer: L = l
-  val io: B = b
 
   // Build a set of Tiles
   val tiles = outer.lazyTiles.map(_.module)
@@ -95,9 +89,8 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
 
   val nCachedPorts = tiles.map(tile => tile.io.cached.size).reduce(_ + _)
   val nUncachedPorts = tiles.map(tile => tile.io.uncached.size).reduce(_ + _)
-  val nBanks = c.nMemChannels * nBanksPerMemChannel
+  val nBanks = nMemChannels * nBanksPerMemChannel
   
-  // Build an uncore backing the Tiles
   buildUncore(p.alterPartial({
     case HastiId => "TL"
     case TLId => "L1toL2"
@@ -105,7 +98,7 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
     case NUncachedTileLinkPorts => nUncachedPorts
   }))
 
-  def buildUncore(implicit p: Parameters) = {
+  def buildUncore(implicit p: Parameters) {
     // Create a simple L1toL2 NoC between the tiles and the banks of outer memory
     // Cached ports are first in client list, making sharerToClientId just an indentity function
     // addrToBank is sed to hash physical addresses (of cache blocks) to banks (and thereby memory channels)
@@ -130,9 +123,10 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
     // and coherence manager(s) to the other side
     l1tol2net.io.clients_cached <> uncoreTileIOs.map(_.cached).flatten
     l1tol2net.io.clients_uncached <> uncoreTileIOs.map(_.uncached).flatten ++ io.slave
-    l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner // legacy goes here (not mmioManager)
+    l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner
+    outer.legacy.module.io.legacy <>  mmioManager.io.outer 
 
-    val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, c.nMemChannels)(outerMemParams))
+    val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, nMemChannels)(outerMemParams))
 
     val backendBuffering = TileLinkDepths(0,0,0,0,0)
     for ((bank, icPort) <- managerEndpoints zip mem_ic.io.in) {
@@ -141,43 +135,80 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
     }
 
     io.master.mem <> mem_ic.io.out
-
-    buildMMIONetwork(TileLinkEnqueuer(mmioManager.io.outer, 1))(outerMMIOParams)
   }
 
-  def buildMMIONetwork(mmio: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
+  for ((tile, i) <- (uncoreTileIOs zipWithIndex)) {
-    val ioAddrMap = globalAddrMap.subMap("io")
+    tile.hartid := UInt(i)
+    tile.resetVector := io.resetVector
+  }
 
-    val cBus = Module(new TileLinkRecursiveInterconnect(1, ioAddrMap))
+  // Coreplex doesn't know when to stop running
-    cBus.io.in.head <> mmio
+  io.success := Bool(false)
+}
+
+trait CoreplexPeripherals extends HasCoreplexParameters {
+  val module: CoreplexPeripheralsModule
+  val l1tol2: TLXbar
+  val legacy: TLLegacy
+  val lazyTiles: Seq[LazyTile]
+
+  val cbus  = LazyModule(new TLXbar)
+  val debug = LazyModule(new TLDebugModule())
+  val plic  = LazyModule(new TLPLIC(() => plicKey))
+  val clint = LazyModule(new CoreplexLocalInterrupter(clintKey))
+
+  cbus.node :=
+    TLAtomicAutomata(arithmetic = true)( // disable once TLB uses TL2 metadata
+    TLWidthWidget(legacy.tlDataBytes)(
+    TLBuffer()(
+    l1tol2.node)))
+
+  debug.node := TLFragmenter(p(XLen)/8, legacy.tlDataBeats * legacy.tlDataBytes)(cbus.node)
+  plic.node  := TLFragmenter(p(XLen)/8, legacy.tlDataBeats * legacy.tlDataBytes)(cbus.node)
+  clint.node := TLFragmenter(p(XLen)/8, legacy.tlDataBeats * legacy.tlDataBytes)(cbus.node)
+
+  lazyTiles.map(_.slave).flatten.foreach { scratch =>
+    scratch  := TLFragmenter(p(XLen)/8, legacy.tlDataBeats * legacy.tlDataBytes)(cbus.node)
+  }
+}
+
+trait CoreplexPeripheralsBundle extends HasCoreplexParameters {
+  val outer: CoreplexPeripherals
+
+  val debug = new DebugBusIO().flip
+  val interrupts = Vec(nExtInterrupts, Bool()).asInput
+}
+
+trait CoreplexPeripheralsModule extends HasCoreplexParameters {
+  val outer: CoreplexPeripherals
+  val io: CoreplexPeripheralsBundle
+  val uncoreTileIOs: Seq[TileIO]
 
-    outer.plicLegacy.module.io.legacy <> cBus.port("cbus:plic")
   for (i <- 0 until io.interrupts.size) {
     val gateway = Module(new LevelGateway)
     gateway.io.interrupt := io.interrupts(i)
     outer.plic.module.io.devices(i) <> gateway.io.plic
   }
 
-    outer.debugLegacy.module.io.legacy <> cBus.port("cbus:debug")
   outer.debug.module.io.db <> io.debug
+  outer.clint.module.io.rtcTick := Counter(p(rocketchip.RTCPeriod)).inc()
 
   // connect coreplex-internal interrupts to tiles
   for ((tile, i) <- (uncoreTileIOs zipWithIndex)) {
-      tile.interrupts <> io.clint(i)
+    tile.interrupts <> outer.clint.module.io.tiles(i)
-      tile.interrupts.meip := outer.plic.module.io.harts(c.plicKey.context(i, 'M'))
+    tile.interrupts.meip := outer.plic.module.io.harts(plicKey.context(i, 'M'))
-      tile.interrupts.seip.foreach(_ := outer.plic.module.io.harts(c.plicKey.context(i, 'S')))
+    tile.interrupts.seip.foreach(_ := outer.plic.module.io.harts(plicKey.context(i, 'S')))
     tile.interrupts.debug := outer.debug.module.io.debugInterrupts(i)
-      tile.hartid := UInt(i)
+  }
-      tile.resetVector := io.resetVector
 }
 
-    val tileSlavePorts = (0 until c.nTiles) map (i => s"cbus:dmem$i") filter (ioAddrMap contains _)
+class BaseCoreplex(implicit p: Parameters) extends BareCoreplex
-    for ((t, m) <- (uncoreTileIOs.map(_.slave).flatten) zip (tileSlavePorts map (cBus port _)))
+    with CoreplexPeripherals {
-      t <> m
+  override lazy val module = new BaseCoreplexModule(this, new BaseCoreplexBundle(this))
-
-    io.master.mmio <> cBus.port("TL2")
 }
 
-  // Coreplex doesn't know when to stop running
+class BaseCoreplexBundle[+L <: BaseCoreplex](outer: L) extends BareCoreplexBundle(outer)
-  io.success := Bool(false)
+    with CoreplexPeripheralsBundle
-}
+
+class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle[L]](outer: L, io: B) extends BareCoreplexModule(outer, io)
+    with CoreplexPeripheralsModule

src/main/scala/coreplex/Coreplex.scala

@@ -18,7 +18,7 @@ trait DirectConnection {
   (tiles zip uncoreTileIOs) foreach { case (tile, uncore) =>
     (uncore.cached zip tile.io.cached) foreach { case (u, t) => u <> TileLinkEnqueuer(t, tlBuffering) }
     (uncore.uncached zip tile.io.uncached) foreach { case (u, t) => u <> TileLinkEnqueuer(t, ultBuffering) }
-    tile.io.slave.foreach { _ <> TileLinkEnqueuer(uncore.slave.get, 1) }
+// !!!    tile.io.slave.foreach { _ <> TileLinkEnqueuer(uncore.slave.get, 1) }
 
     tile.io.interrupts <> uncore.interrupts
 
@@ -27,21 +27,19 @@ trait DirectConnection {
   }
 }
 
-class DefaultCoreplex(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplex(c)(p) {
+class DefaultCoreplex(implicit p: Parameters) extends BaseCoreplex {
-  override lazy val module = Module(new DefaultCoreplexModule(c, this, new DefaultCoreplexBundle(c)(p))(p))
+  override lazy val module = new DefaultCoreplexModule(this, new DefaultCoreplexBundle(this))
 }
 
-class DefaultCoreplexBundle(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplexBundle(c)(p)
+class DefaultCoreplexBundle[+L <: DefaultCoreplex](outer: L) extends BaseCoreplexBundle(outer)
 
-class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle](
+class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle[L]](outer: L, io: B) extends BaseCoreplexModule(outer, io)
-    c: CoreplexConfig, l: L, b: B)(implicit p: Parameters) extends BaseCoreplexModule(c, l, b)(p)
     with DirectConnection
 
 /////
 
-trait TileClockResetBundle {
+trait TileClockResetBundle extends HasCoreplexParameters {
-  val c: CoreplexConfig
+  val tcrs = Vec(nTiles, new Bundle {
-  val tcrs = Vec(c.nTiles, new Bundle {
     val clock = Clock(INPUT)
     val reset = Bool(INPUT)
   })
@@ -58,7 +56,7 @@ trait AsyncConnection {
 
     (uncore.cached zip tile.io.cached) foreach { case (u, t) => u <> AsyncTileLinkFrom(tcr.clock, tcr.reset, t) }
     (uncore.uncached zip tile.io.uncached) foreach { case (u, t) => u <> AsyncUTileLinkFrom(tcr.clock, tcr.reset, t) }
-    tile.io.slave.foreach { _ <> AsyncUTileLinkTo(tcr.clock, tcr.reset, uncore.slave.get)}
+// !!!    tile.io.slave.foreach { _ <> AsyncUTileLinkTo(tcr.clock, tcr.reset, uncore.slave.get)}
 
     val ti = tile.io.interrupts
     val ui = uncore.interrupts
@@ -73,13 +71,12 @@ trait AsyncConnection {
   }
 }
 
-class MultiClockCoreplex(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplex(c)(p) {
+class MultiClockCoreplex(implicit p: Parameters) extends BaseCoreplex {
-  override lazy val module = Module(new MultiClockCoreplexModule(c, this, new MultiClockCoreplexBundle(c)(p))(p))
+  override lazy val module = new MultiClockCoreplexModule(this, new MultiClockCoreplexBundle(this))
 }
 
-class MultiClockCoreplexBundle(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplexBundle(c)(p)
+class MultiClockCoreplexBundle[+L <: MultiClockCoreplex](outer: L) extends BaseCoreplexBundle(outer)
     with TileClockResetBundle
 
-class MultiClockCoreplexModule[+L <: MultiClockCoreplex, +B <: MultiClockCoreplexBundle](
+class MultiClockCoreplexModule[+L <: MultiClockCoreplex, +B <: MultiClockCoreplexBundle[L]](outer: L, io: B) extends BaseCoreplexModule(outer, io)
-    c: CoreplexConfig, l: L, b: B)(implicit p: Parameters) extends BaseCoreplexModule(c, l, b)(p)
     with AsyncConnection

src/main/scala/groundtest/Configs.scala

@@ -72,8 +72,6 @@ class Edge32BitMemtestConfig extends Config(
 /* Composable Configs to set individual parameters */
 class WithGroundTest extends Config(
   (pname, site, here) => pname match {
-    case BuildCoreplex =>
-      (c: CoreplexConfig, p: Parameters) => LazyModule(new GroundTestCoreplex(c)(p)).module
     case TLKey("L1toL2") => {
       val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
       val dataBeats = (8 * site(CacheBlockBytes)) / site(XLen)
@@ -106,7 +104,7 @@ class WithGroundTest extends Config(
       }
     }
     case BuildExampleTop =>
-      (p: Parameters) => LazyModule(new ExampleTopWithTestRAM(p))
+      (p: Parameters) => LazyModule(new ExampleTopWithTestRAM(new GroundTestCoreplex()(_))(p))
     case FPUKey => None
     case UseAtomics => false
     case UseCompressed => false

src/main/scala/groundtest/Coreplex.scala

@@ -4,13 +4,13 @@ import Chisel._
 import cde.{Parameters}
 import coreplex._
 
-class GroundTestCoreplex(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplex(c)(p) {
+class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex {
-  override lazy val module = Module(new GroundTestCoreplexModule(c, this, new GroundTestCoreplexBundle(c)(p))(p))
+  override lazy val module = new GroundTestCoreplexModule(this, new GroundTestCoreplexBundle(this))
 }
 
-class GroundTestCoreplexBundle(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplexBundle(c)(p)
+class GroundTestCoreplexBundle[+L <: GroundTestCoreplex](outer: L) extends BaseCoreplexBundle(outer)
 
-class GroundTestCoreplexModule[+L <: GroundTestCoreplex, +B <: GroundTestCoreplexBundle](
+class GroundTestCoreplexModule[+L <: GroundTestCoreplex, +B <: GroundTestCoreplexBundle[L]](outer: L, io: B) extends BaseCoreplexModule(outer, io)
-    c: CoreplexConfig, l: L, b: B)(implicit p: Parameters) extends BaseCoreplexModule(c, l, b)(p) with DirectConnection {
+    with DirectConnection {
   io.success := tiles.flatMap(_.io.elements get "success").map(_.asInstanceOf[Bool]).reduce(_&&_)
 }

src/main/scala/groundtest/Tile.scala

@@ -97,6 +97,7 @@ abstract class GroundTest(implicit val p: Parameters) extends Module
 }
 
 class GroundTestTile(implicit val p: Parameters) extends LazyTile with HasGroundTestParameters {
+  val slave = None
   lazy val module = new TileImp(this) {
     val io = new TileIO(bc) {
       val success = Bool(OUTPUT)

src/main/scala/rocket/dcache.scala

@@ -497,7 +497,7 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
   }
 }
 
-class ScratchpadSlavePort(implicit p: Parameters) extends LazyModule {
+class ScratchpadSlavePort(implicit val p: Parameters) extends LazyModule with HasCoreParameters {
   val beatBytes = p(XLen)/8
   val node = TLManagerNode(TLManagerPortParameters(
     Seq(TLManagerParameters(
@@ -510,7 +510,7 @@ class ScratchpadSlavePort(implicit p: Parameters) extends LazyModule {
     beatBytes = beatBytes,
     minLatency = 1))
 
-  lazy val module = new LazyModuleImp(this) with HasCoreParameters {
+  lazy val module = new LazyModuleImp(this) {
     val io = new Bundle {
       val tl_in = node.bundleIn
       val dmem = new HellaCacheIO

src/main/scala/rocket/tile.scala

@@ -54,6 +54,7 @@ abstract class LazyTile(implicit p: Parameters) extends LazyModule {
     xLen = p(XLen))
 
   val module: TileImp
+  val slave: Option[TLOutputNode]
 }
 
 class RocketTile(implicit p: Parameters) extends LazyTile {

src/main/scala/rocketchip/BaseTop.scala

@@ -17,13 +17,12 @@ import coreplex._
 case object GlobalAddrMap extends Field[AddrMap]
 case object ConfigString extends Field[String]
 case object NCoreplexExtClients extends Field[Int]
+case object NExtInterrupts extends Field[Int]
 /** Enable or disable monitoring of Diplomatic buses */
 case object TLEmitMonitors extends Field[Bool]
-/** Function for building Coreplex */
-case object BuildCoreplex extends Field[(CoreplexConfig, Parameters) => BaseCoreplexModule[BaseCoreplex, BaseCoreplexBundle]]
 
 /** Base Top with no Periphery */
-abstract class BaseTop(q: Parameters) extends LazyModule {
+abstract class BaseTop[+C <: BaseCoreplex](buildCoreplex: Parameters => C)(implicit q: Parameters) extends LazyModule {
   // the following variables will be refactored properly with TL2
   val pInterrupts = new RangeManager
   val pBusMasters = new RangeManager
@@ -35,52 +34,39 @@ abstract class BaseTop(q: Parameters) extends LazyModule {
   val peripheryBus = LazyModule(new TLXbar)
   lazy val peripheryManagers = socBus.node.edgesIn(0).manager.managers
 
-  lazy val c = CoreplexConfig(
+  // Fill in the TL1 legacy parameters
-    nTiles = q(NTiles),
+  val qWithSums = q.alterPartial {
-    nExtInterrupts = pInterrupts.sum,
+    case NCoreplexExtClients => pBusMasters.sum
-    nSlaves = pBusMasters.sum,
+    case NExtInterrupts => pInterrupts.sum
-    nMemChannels = q(NMemoryChannels),
+  }
-    hasSupervisor = q(UseVM)
+  val qWithMap = qWithSums.alterPartial {
-  )
+     case GlobalAddrMap => GenerateGlobalAddrMap(qWithSums, peripheryManagers)
+  }
+  implicit val p = qWithMap.alterPartial {
+    case ConfigString => GenerateConfigString(qWithMap, peripheryManagers)
+  }
 
-  lazy val genGlobalAddrMap = GenerateGlobalAddrMap(q, peripheryManagers)
+  val coreplex = LazyModule(buildCoreplex(p))
-  private val qWithMap = q.alterPartial({case GlobalAddrMap => genGlobalAddrMap})
-
-  lazy val genConfigString = GenerateConfigString(qWithMap, c, peripheryManagers)
-  implicit val p = qWithMap.alterPartial({
-    case ConfigString => genConfigString
-    case NCoreplexExtClients => pBusMasters.sum})
-
-  val legacy = LazyModule(new TLLegacy()(p.alterPartial({ case TLId => "L2toMMIO" })))
 
   peripheryBus.node :=
-    TLWidthWidget(p(SOCBusKey).beatBytes)(
     TLBuffer()(
     TLAtomicAutomata(arithmetic = p(PeripheryBusKey).arithAMO)(
+    TLWidthWidget(p(SOCBusKey).beatBytes)(
     socBus.node)))
 
-  socBus.node :=
+  socBus.node := coreplex.mmio
-    TLWidthWidget(legacy.tlDataBytes)(
-    TLHintHandler()(
-    legacy.node))
 
   TopModule.contents = Some(this)
 }
 
-abstract class BaseTopBundle[+L <: BaseTop](
+abstract class BaseTopBundle[+L <: BaseTop[BaseCoreplex]](val outer: L) extends Bundle {
-    val p: Parameters,
+  implicit val p = outer.p
-    val outer: L) extends Bundle {
   val success = Bool(OUTPUT)
 }
 
-abstract class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle[L]](
+abstract class BaseTopModule[+L <: BaseTop[BaseCoreplex], +B <: BaseTopBundle[L]](val outer: L, val io: B) extends LazyModuleImp(outer) {
-    val p: Parameters,
+  implicit val p = outer.p
-    val outer: L,
+  val coreplexIO = Wire(outer.coreplex.module.io)
-    val io: B) extends LazyModuleImp(outer) {
-  val coreplex = p(BuildCoreplex)(outer.c, p)
-  val coreplexIO = Wire(coreplex.io)
-
-  outer.legacy.module.io.legacy <> coreplexIO.master.mmio
 
   println("Generated Address Map")
   for (entry <- p(GlobalAddrMap).flatten) {
@@ -106,8 +92,8 @@ abstract class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle[L]](
 }
 
 trait DirectConnection {
-  val coreplexIO: BaseCoreplexBundle
+  val coreplexIO: BaseCoreplexBundle[BaseCoreplex]
-  val coreplex: BaseCoreplexModule[BaseCoreplex, BaseCoreplexBundle]
+  val outer: BaseTop[BaseCoreplex]
 
-  coreplexIO <> coreplex.io
+  coreplexIO <> outer.coreplex.module.io
 }

src/main/scala/rocketchip/Configs.scala

@@ -40,8 +40,6 @@ class BasePlatformConfig extends Config(
           site(TLKey("L2toMC")).copy(dataBeats = edgeDataBeats)
         case TLKey("MMIOtoEdge") =>
           site(TLKey("L2toMMIO")).copy(dataBeats = edgeDataBeats)
-        case BuildCoreplex =>
-          (c: CoreplexConfig, p: Parameters) => LazyModule(new DefaultCoreplex(c)(p)).module
         case NExtTopInterrupts => 2
         case SOCBusKey => SOCBusConfig(beatBytes = site(TLKey("L2toMMIO")).dataBitsPerBeat/8)
         case PeripheryBusKey => PeripheryBusConfig(arithAMO = true, beatBytes = 4)
@@ -65,7 +63,7 @@ class BasePlatformConfig extends Config(
         case ExtMemSize => Dump("MEM_SIZE", 0x10000000L)
         case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
         case BuildExampleTop =>
-          (p: Parameters) => LazyModule(new ExampleTop(p))
+          (p: Parameters) => LazyModule(new ExampleTop(new DefaultCoreplex()(_))(p))
         case SimMemLatency => 0
         case _ => throw new CDEMatchError
       }

src/main/scala/rocketchip/ExampleTop.scala

@@ -9,17 +9,17 @@ import coreplex._
 import rocketchip._
 
 /** Example Top with Periphery */
-class ExampleTop(q: Parameters) extends BaseTop(q)
+class ExampleTop[+C <: BaseCoreplex](buildCoreplex: Parameters => C)(implicit p: Parameters) extends BaseTop(buildCoreplex)
     with PeripheryBootROM
     with PeripheryDebug
     with PeripheryExtInterrupts
     with PeripheryMasterMem
     with PeripheryMasterAXI4MMIO
     with PeripherySlave {
-  override lazy val module = Module(new ExampleTopModule(p, this, new ExampleTopBundle(p, this)))
+  override lazy val module = new ExampleTopModule(this, new ExampleTopBundle(this))
 }
 
-class ExampleTopBundle[+L <: ExampleTop](p: Parameters, l: L) extends BaseTopBundle(p, l)
+class ExampleTopBundle[+L <: ExampleTop[BaseCoreplex]](outer: L) extends BaseTopBundle(outer)
     with PeripheryBootROMBundle
     with PeripheryDebugBundle
     with PeripheryExtInterruptsBundle
@@ -27,7 +27,7 @@ class ExampleTopBundle[+L <: ExampleTop](p: Parameters, l: L) extends BaseTopBun
     with PeripheryMasterAXI4MMIOBundle
     with PeripherySlaveBundle
 
-class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle[L]](p: Parameters, l: L, b: B) extends BaseTopModule(p, l, b)
+class ExampleTopModule[+L <: ExampleTop[BaseCoreplex], +B <: ExampleTopBundle[L]](outer: L, io: B) extends BaseTopModule(outer, io)
     with PeripheryBootROMModule
     with PeripheryDebugModule
     with PeripheryExtInterruptsModule
@@ -38,13 +38,13 @@ class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle[L]](p: Parameter
     with DirectConnection
 
 /** Example Top with TestRAM */
-class ExampleTopWithTestRAM(q: Parameters) extends ExampleTop(q)
+class ExampleTopWithTestRAM[+C <: BaseCoreplex](buildCoreplex: Parameters => C)(implicit p: Parameters) extends ExampleTop(buildCoreplex)
     with PeripheryTestRAM {
-  override lazy val module = Module(new ExampleTopWithTestRAMModule(p, this, new ExampleTopWithTestRAMBundle(p, this)))
+  override lazy val module = new ExampleTopWithTestRAMModule(this, new ExampleTopWithTestRAMBundle(this))
 }
 
-class ExampleTopWithTestRAMBundle[+L <: ExampleTopWithTestRAM](p: Parameters, l: L) extends ExampleTopBundle(p, l)
+class ExampleTopWithTestRAMBundle[+L <: ExampleTopWithTestRAM[BaseCoreplex]](outer: L) extends ExampleTopBundle(outer)
     with PeripheryTestRAMBundle
 
-class ExampleTopWithTestRAMModule[+L <: ExampleTopWithTestRAM, +B <: ExampleTopWithTestRAMBundle[L]](p: Parameters, l: L, b: B) extends ExampleTopModule(p, l, b)
+class ExampleTopWithTestRAMModule[+L <: ExampleTopWithTestRAM[BaseCoreplex], +B <: ExampleTopWithTestRAMBundle[L]](outer: L, io: B) extends ExampleTopModule(outer, io)
     with PeripheryTestRAMModule

src/main/scala/rocketchip/Periphery.scala

@@ -110,7 +110,7 @@ trait PeripheryDebugModule {
   implicit val p: Parameters
   val outer: PeripheryDebug
   val io: PeripheryDebugBundle
-  val coreplexIO: BaseCoreplexBundle
+  val coreplexIO: BaseCoreplexBundle[BaseCoreplex]
 
   if (p(IncludeJtagDTM)) {
     // JtagDTMWithSync is a wrapper which
@@ -143,7 +143,7 @@ trait PeripheryExtInterruptsModule {
   implicit val p: Parameters
   val outer: PeripheryExtInterrupts
   val io: PeripheryExtInterruptsBundle
-  val coreplexIO: BaseCoreplexBundle
+  val coreplexIO: BaseCoreplexBundle[BaseCoreplex]
 
   {
     val r = outer.pInterrupts.range("ext")
@@ -172,7 +172,7 @@ trait PeripheryMasterMemModule extends HasPeripheryParameters {
   implicit val p: Parameters
   val outer: PeripheryMasterMem
   val io: PeripheryMasterMemBundle
-  val coreplexIO: BaseCoreplexBundle
+  val coreplexIO: BaseCoreplexBundle[BaseCoreplex]
 
   val edgeMem = coreplexIO.master.mem.map(TileLinkWidthAdapter(_, edgeMemParams))
 
@@ -199,8 +199,9 @@ trait PeripheryMasterMemModule extends HasPeripheryParameters {
 /////
 
 // PeripheryMasterAXI4MMIO is an example, make your own cake pattern like this one.
-trait PeripheryMasterAXI4MMIO extends BaseTop with HasPeripheryParameters {
+trait PeripheryMasterAXI4MMIO extends HasPeripheryParameters {
   implicit val p: Parameters
+  val socBus: TLXbar
 
   val mmio_axi4 = AXI4BlindOutputNode(AXI4SlavePortParameters(
     slaves = Seq(AXI4SlaveParameters(
@@ -253,7 +254,7 @@ trait PeripherySlaveModule extends HasPeripheryParameters {
   implicit val p: Parameters
   val outer: PeripherySlave
   val io: PeripherySlaveBundle
-  val coreplexIO: BaseCoreplexBundle
+  val coreplexIO: BaseCoreplexBundle[BaseCoreplex]
 
   if (p(NExtBusAXIChannels) > 0) {
     val arb = Module(new NastiArbiter(p(NExtBusAXIChannels)))
@@ -339,6 +340,6 @@ trait PeripheryTestBusMasterModule {
 /////
 
 trait HardwiredResetVector {
-  val coreplexIO: BaseCoreplexBundle
+  val coreplexIO: BaseCoreplexBundle[BaseCoreplex]
   coreplexIO.resetVector := UInt(0x1000) // boot ROM
 }

src/main/scala/rocketchip/TestHarness.scala

@@ -8,14 +8,14 @@ import junctions._
 import junctions.NastiConstants._
 import util.LatencyPipe
 
-case object BuildExampleTop extends Field[Parameters => ExampleTop]
+case object BuildExampleTop extends Field[Parameters => ExampleTop[coreplex.BaseCoreplex]]
 case object SimMemLatency extends Field[Int]
 
 class TestHarness(q: Parameters) extends Module {
   val io = new Bundle {
     val success = Bool(OUTPUT)
   }
-  val dut = q(BuildExampleTop)(q).module
+  val dut = Module(q(BuildExampleTop)(q).module)
   implicit val p = dut.p
 
   // This test harness isn't especially flexible yet

src/main/scala/rocketchip/Utils.scala

@@ -104,7 +104,8 @@ object GenerateGlobalAddrMap {
 }
 
 object GenerateConfigString {
-  def apply(p: Parameters, c: CoreplexConfig, peripheryManagers: Seq[TLManagerParameters]) = {
+  def apply(p: Parameters, peripheryManagers: Seq[TLManagerParameters]) = {
+    val c = CoreplexParameters()(p)
     val addrMap = p(GlobalAddrMap)
     val plicAddr = addrMap("io:cbus:plic").start
     val clint = CoreplexLocalInterrupterConfig()