riscv/rocket-chip
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rocketchip: move TL2 and cake pattern into Coreplex

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This commit is contained in:
Wesley W. Terpstra
2016-10-26 22:28:40 -07:00
parent 89139a9492
commit 825c253a72
13 changed files with 173 additions and 159 deletions
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3
src/main/scala/rocketchip/Utils.scala
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@ -104,7 +104,8 @@ object GenerateGlobalAddrMap {
}
object GenerateConfigString {
def apply(p: Parameters, c: CoreplexConfig, peripheryManagers: Seq[TLManagerParameters]) = {
def apply(p: Parameters, peripheryManagers: Seq[TLManagerParameters]) = {
val c = CoreplexParameters()(p)
val addrMap = p(GlobalAddrMap)
val plicAddr = addrMap("io:cbus:plic").start
val clint = CoreplexLocalInterrupterConfig()