riscv/rocket-chip
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rocketchip: move TL2 and cake pattern into Coreplex

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This commit is contained in:
Wesley W. Terpstra
2016-10-26 22:28:40 -07:00
parent 89139a9492
commit 825c253a72
13 changed files with 173 additions and 159 deletions
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4
src/main/scala/rocket/dcache.scala
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@ -497,7 +497,7 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
}
}
class ScratchpadSlavePort(implicit p: Parameters) extends LazyModule {
class ScratchpadSlavePort(implicit val p: Parameters) extends LazyModule with HasCoreParameters {
val beatBytes = p(XLen)/8
val node = TLManagerNode(TLManagerPortParameters(
Seq(TLManagerParameters(
@ -510,7 +510,7 @@ class ScratchpadSlavePort(implicit p: Parameters) extends LazyModule {
beatBytes = beatBytes,
minLatency = 1))
lazy val module = new LazyModuleImp(this) with HasCoreParameters {
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val tl_in = node.bundleIn
val dmem = new HellaCacheIO