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rocketchip: move TL2 and cake pattern into Coreplex

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This commit is contained in:
Wesley W. Terpstra
2016-10-26 22:28:40 -07:00
parent 89139a9492
commit 825c253a72
13 changed files with 173 additions and 159 deletions
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4
src/main/scala/groundtest/Configs.scala
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@ -72,8 +72,6 @@ class Edge32BitMemtestConfig extends Config(
/* Composable Configs to set individual parameters */
class WithGroundTest extends Config(
(pname, site, here) => pname match {
case BuildCoreplex =>
(c: CoreplexConfig, p: Parameters) => LazyModule(new GroundTestCoreplex(c)(p)).module
case TLKey("L1toL2") => {
val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
val dataBeats = (8 * site(CacheBlockBytes)) / site(XLen)
@ -106,7 +104,7 @@ class WithGroundTest extends Config(
}
}
case BuildExampleTop =>
(p: Parameters) => LazyModule(new ExampleTopWithTestRAM(p))
(p: Parameters) => LazyModule(new ExampleTopWithTestRAM(new GroundTestCoreplex()(_))(p))
case FPUKey => None
case UseAtomics => false
case UseCompressed => false