rocketchip: move TL2 and cake pattern into Coreplex
This commit is contained in:
@ -72,8 +72,6 @@ class Edge32BitMemtestConfig extends Config(
|
||||
/* Composable Configs to set individual parameters */
|
||||
class WithGroundTest extends Config(
|
||||
(pname, site, here) => pname match {
|
||||
case BuildCoreplex =>
|
||||
(c: CoreplexConfig, p: Parameters) => LazyModule(new GroundTestCoreplex(c)(p)).module
|
||||
case TLKey("L1toL2") => {
|
||||
val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
|
||||
val dataBeats = (8 * site(CacheBlockBytes)) / site(XLen)
|
||||
@ -106,7 +104,7 @@ class WithGroundTest extends Config(
|
||||
}
|
||||
}
|
||||
case BuildExampleTop =>
|
||||
(p: Parameters) => LazyModule(new ExampleTopWithTestRAM(p))
|
||||
(p: Parameters) => LazyModule(new ExampleTopWithTestRAM(new GroundTestCoreplex()(_))(p))
|
||||
case FPUKey => None
|
||||
case UseAtomics => false
|
||||
case UseCompressed => false
|
||||
|
@ -4,13 +4,13 @@ import Chisel._
|
||||
import cde.{Parameters}
|
||||
import coreplex._
|
||||
|
||||
class GroundTestCoreplex(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplex(c)(p) {
|
||||
override lazy val module = Module(new GroundTestCoreplexModule(c, this, new GroundTestCoreplexBundle(c)(p))(p))
|
||||
class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex {
|
||||
override lazy val module = new GroundTestCoreplexModule(this, new GroundTestCoreplexBundle(this))
|
||||
}
|
||||
|
||||
class GroundTestCoreplexBundle(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplexBundle(c)(p)
|
||||
class GroundTestCoreplexBundle[+L <: GroundTestCoreplex](outer: L) extends BaseCoreplexBundle(outer)
|
||||
|
||||
class GroundTestCoreplexModule[+L <: GroundTestCoreplex, +B <: GroundTestCoreplexBundle](
|
||||
c: CoreplexConfig, l: L, b: B)(implicit p: Parameters) extends BaseCoreplexModule(c, l, b)(p) with DirectConnection {
|
||||
class GroundTestCoreplexModule[+L <: GroundTestCoreplex, +B <: GroundTestCoreplexBundle[L]](outer: L, io: B) extends BaseCoreplexModule(outer, io)
|
||||
with DirectConnection {
|
||||
io.success := tiles.flatMap(_.io.elements get "success").map(_.asInstanceOf[Bool]).reduce(_&&_)
|
||||
}
|
||||
|
@ -97,6 +97,7 @@ abstract class GroundTest(implicit val p: Parameters) extends Module
|
||||
}
|
||||
|
||||
class GroundTestTile(implicit val p: Parameters) extends LazyTile with HasGroundTestParameters {
|
||||
val slave = None
|
||||
lazy val module = new TileImp(this) {
|
||||
val io = new TileIO(bc) {
|
||||
val success = Bool(OUTPUT)
|
||||
|
Reference in New Issue
Block a user