rocketchip: move TL2 and cake pattern into Coreplex
This commit is contained in:
Wesley W. Terpstra
@ -35,59 +35,53 @@ trait HasCoreplexParameters {
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lazy val outerMemParams = p.alterPartial({ case TLId => "L2toMC" })
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lazy val outerMMIOParams = p.alterPartial({ case TLId => "L2toMMIO" })
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lazy val globalAddrMap = p(rocketchip.GlobalAddrMap)
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lazy val nTiles = p(uncore.devices.NTiles)
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lazy val nExtInterrupts = p(rocketchip.NExtInterrupts)
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lazy val nSlaves = p(rocketchip.NCoreplexExtClients)
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lazy val nMemChannels = p(NMemoryChannels)
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lazy val hasSupervisor = p(rocket.UseVM)
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lazy val nInterruptPriorities = if (nExtInterrupts <= 1) 0 else (nExtInterrupts min 7)
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lazy val plicKey = PLICConfig(nTiles, hasSupervisor, nExtInterrupts, nInterruptPriorities)
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lazy val clintKey = CoreplexLocalInterrupterConfig()
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}
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case class CoreplexConfig(
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nTiles: Int,
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nExtInterrupts: Int,
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nSlaves: Int,
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nMemChannels: Int,
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hasSupervisor: Boolean)
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{
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val nInterruptPriorities = if (nExtInterrupts <= 1) 0 else (nExtInterrupts min 7)
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val plicKey = PLICConfig(nTiles, hasSupervisor, nExtInterrupts, nInterruptPriorities)
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}
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case class CoreplexParameters(implicit val p: Parameters) extends HasCoreplexParameters
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abstract class BaseCoreplex(c: CoreplexConfig)(implicit val p: Parameters) extends LazyModule with HasCoreplexParameters {
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abstract class BareCoreplex(implicit val p: Parameters) extends LazyModule with HasCoreplexParameters {
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val l1tol2 = LazyModule(new TLXbar)
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val mmio = TLOutputNode()
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val lazyTiles = p(BuildTiles) map { _(p) }
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val legacy = LazyModule(new TLLegacy()(outerMMIOParams))
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val debugLegacy = LazyModule(new TLLegacy()(outerMMIOParams))
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val debug = LazyModule(new TLDebugModule())
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debug.node :=
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TLHintHandler()(
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mmio :=
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TLBuffer()(
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TLFragmenter(p(XLen)/8, debugLegacy.tlDataBeats * debugLegacy.tlDataBytes)(
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TLWidthWidget(debugLegacy.tlDataBytes)(debugLegacy.node))))
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val plicLegacy = LazyModule(new TLLegacy()(outerMMIOParams))
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val plic = LazyModule(new TLPLIC(c.plicKey))
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plic.node :=
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TLHintHandler()(
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TLBuffer()(
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TLFragmenter(p(XLen)/8, plicLegacy.tlDataBeats * plicLegacy.tlDataBytes)(
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TLWidthWidget(plicLegacy.tlDataBytes)(plicLegacy.node))))
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TLWidthWidget(legacy.tlDataBytes)(
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l1tol2.node))
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// Kill this once we move TL2 into rocket
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l1tol2.node :=
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TLHintHandler()(
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legacy.node)
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}
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abstract class BaseCoreplexBundle(val c: CoreplexConfig)(implicit val p: Parameters) extends Bundle with HasCoreplexParameters {
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abstract class BareCoreplexBundle[+L <: BareCoreplex](val outer: L) extends Bundle with HasCoreplexParameters {
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implicit val p = outer.p
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val master = new Bundle {
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val mem = Vec(c.nMemChannels, new ClientUncachedTileLinkIO()(outerMemParams))
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val mmio = new ClientUncachedTileLinkIO()(outerMMIOParams)
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val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outerMemParams))
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val mmio = outer.mmio.bundleOut
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}
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val slave = Vec(c.nSlaves, new ClientUncachedTileLinkIO()(innerParams)).flip
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val interrupts = Vec(c.nExtInterrupts, Bool()).asInput
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val debug = new DebugBusIO()(p).flip
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val clint = Vec(c.nTiles, new CoreplexLocalInterrupts).asInput
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val slave = Vec(nSlaves, new ClientUncachedTileLinkIO()(innerParams)).flip
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val resetVector = UInt(INPUT, p(XLen))
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val success = Bool(OUTPUT) // used for testing
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override def cloneType = this.getClass.getConstructors.head.newInstance(c, p).asInstanceOf[this.type]
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override def cloneType = this.getClass.getConstructors.head.newInstance(outer).asInstanceOf[this.type]
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}
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abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
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c: CoreplexConfig, l: L, b: B)(implicit val p: Parameters) extends LazyModuleImp(l) with HasCoreplexParameters {
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val outer: L = l
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val io: B = b
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abstract class BareCoreplexModule[+L <: BareCoreplex, +B <: BareCoreplexBundle[L]](val outer: L, val io: B) extends LazyModuleImp(outer) with HasCoreplexParameters {
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implicit val p = outer.p
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// Build a set of Tiles
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val tiles = outer.lazyTiles.map(_.module)
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@ -95,9 +89,8 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
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val nCachedPorts = tiles.map(tile => tile.io.cached.size).reduce(_ + _)
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val nUncachedPorts = tiles.map(tile => tile.io.uncached.size).reduce(_ + _)
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val nBanks = c.nMemChannels * nBanksPerMemChannel
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// Build an uncore backing the Tiles
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val nBanks = nMemChannels * nBanksPerMemChannel
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buildUncore(p.alterPartial({
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case HastiId => "TL"
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case TLId => "L1toL2"
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@ -105,7 +98,7 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
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case NUncachedTileLinkPorts => nUncachedPorts
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}))
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def buildUncore(implicit p: Parameters) = {
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def buildUncore(implicit p: Parameters) {
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// Create a simple L1toL2 NoC between the tiles and the banks of outer memory
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// Cached ports are first in client list, making sharerToClientId just an indentity function
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// addrToBank is sed to hash physical addresses (of cache blocks) to banks (and thereby memory channels)
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@ -130,9 +123,10 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
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// and coherence manager(s) to the other side
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l1tol2net.io.clients_cached <> uncoreTileIOs.map(_.cached).flatten
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l1tol2net.io.clients_uncached <> uncoreTileIOs.map(_.uncached).flatten ++ io.slave
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l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner // legacy goes here (not mmioManager)
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l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner
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outer.legacy.module.io.legacy <> mmioManager.io.outer
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val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, c.nMemChannels)(outerMemParams))
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val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, nMemChannels)(outerMemParams))
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val backendBuffering = TileLinkDepths(0,0,0,0,0)
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for ((bank, icPort) <- managerEndpoints zip mem_ic.io.in) {
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@ -141,43 +135,80 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
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}
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io.master.mem <> mem_ic.io.out
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buildMMIONetwork(TileLinkEnqueuer(mmioManager.io.outer, 1))(outerMMIOParams)
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}
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def buildMMIONetwork(mmio: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
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val ioAddrMap = globalAddrMap.subMap("io")
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val cBus = Module(new TileLinkRecursiveInterconnect(1, ioAddrMap))
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cBus.io.in.head <> mmio
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outer.plicLegacy.module.io.legacy <> cBus.port("cbus:plic")
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for (i <- 0 until io.interrupts.size) {
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val gateway = Module(new LevelGateway)
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gateway.io.interrupt := io.interrupts(i)
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outer.plic.module.io.devices(i) <> gateway.io.plic
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}
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outer.debugLegacy.module.io.legacy <> cBus.port("cbus:debug")
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outer.debug.module.io.db <> io.debug
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// connect coreplex-internal interrupts to tiles
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for ((tile, i) <- (uncoreTileIOs zipWithIndex)) {
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tile.interrupts <> io.clint(i)
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tile.interrupts.meip := outer.plic.module.io.harts(c.plicKey.context(i, 'M'))
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tile.interrupts.seip.foreach(_ := outer.plic.module.io.harts(c.plicKey.context(i, 'S')))
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tile.interrupts.debug := outer.debug.module.io.debugInterrupts(i)
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tile.hartid := UInt(i)
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tile.resetVector := io.resetVector
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}
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val tileSlavePorts = (0 until c.nTiles) map (i => s"cbus:dmem$i") filter (ioAddrMap contains _)
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for ((t, m) <- (uncoreTileIOs.map(_.slave).flatten) zip (tileSlavePorts map (cBus port _)))
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t <> m
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io.master.mmio <> cBus.port("TL2")
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for ((tile, i) <- (uncoreTileIOs zipWithIndex)) {
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tile.hartid := UInt(i)
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tile.resetVector := io.resetVector
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}
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// Coreplex doesn't know when to stop running
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io.success := Bool(false)
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}
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trait CoreplexPeripherals extends HasCoreplexParameters {
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val module: CoreplexPeripheralsModule
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val l1tol2: TLXbar
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val legacy: TLLegacy
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val lazyTiles: Seq[LazyTile]
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val cbus = LazyModule(new TLXbar)
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val debug = LazyModule(new TLDebugModule())
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val plic = LazyModule(new TLPLIC(() => plicKey))
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val clint = LazyModule(new CoreplexLocalInterrupter(clintKey))
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cbus.node :=
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TLAtomicAutomata(arithmetic = true)( // disable once TLB uses TL2 metadata
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TLWidthWidget(legacy.tlDataBytes)(
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TLBuffer()(
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l1tol2.node)))
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debug.node := TLFragmenter(p(XLen)/8, legacy.tlDataBeats * legacy.tlDataBytes)(cbus.node)
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plic.node := TLFragmenter(p(XLen)/8, legacy.tlDataBeats * legacy.tlDataBytes)(cbus.node)
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clint.node := TLFragmenter(p(XLen)/8, legacy.tlDataBeats * legacy.tlDataBytes)(cbus.node)
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lazyTiles.map(_.slave).flatten.foreach { scratch =>
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scratch := TLFragmenter(p(XLen)/8, legacy.tlDataBeats * legacy.tlDataBytes)(cbus.node)
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}
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}
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trait CoreplexPeripheralsBundle extends HasCoreplexParameters {
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val outer: CoreplexPeripherals
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val debug = new DebugBusIO().flip
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val interrupts = Vec(nExtInterrupts, Bool()).asInput
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}
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trait CoreplexPeripheralsModule extends HasCoreplexParameters {
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val outer: CoreplexPeripherals
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val io: CoreplexPeripheralsBundle
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val uncoreTileIOs: Seq[TileIO]
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for (i <- 0 until io.interrupts.size) {
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val gateway = Module(new LevelGateway)
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gateway.io.interrupt := io.interrupts(i)
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outer.plic.module.io.devices(i) <> gateway.io.plic
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}
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outer.debug.module.io.db <> io.debug
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outer.clint.module.io.rtcTick := Counter(p(rocketchip.RTCPeriod)).inc()
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// connect coreplex-internal interrupts to tiles
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for ((tile, i) <- (uncoreTileIOs zipWithIndex)) {
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tile.interrupts <> outer.clint.module.io.tiles(i)
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tile.interrupts.meip := outer.plic.module.io.harts(plicKey.context(i, 'M'))
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tile.interrupts.seip.foreach(_ := outer.plic.module.io.harts(plicKey.context(i, 'S')))
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tile.interrupts.debug := outer.debug.module.io.debugInterrupts(i)
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}
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}
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class BaseCoreplex(implicit p: Parameters) extends BareCoreplex
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with CoreplexPeripherals {
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override lazy val module = new BaseCoreplexModule(this, new BaseCoreplexBundle(this))
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}
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class BaseCoreplexBundle[+L <: BaseCoreplex](outer: L) extends BareCoreplexBundle(outer)
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with CoreplexPeripheralsBundle
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class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle[L]](outer: L, io: B) extends BareCoreplexModule(outer, io)
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with CoreplexPeripheralsModule
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@ -18,7 +18,7 @@ trait DirectConnection {
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(tiles zip uncoreTileIOs) foreach { case (tile, uncore) =>
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(uncore.cached zip tile.io.cached) foreach { case (u, t) => u <> TileLinkEnqueuer(t, tlBuffering) }
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(uncore.uncached zip tile.io.uncached) foreach { case (u, t) => u <> TileLinkEnqueuer(t, ultBuffering) }
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tile.io.slave.foreach { _ <> TileLinkEnqueuer(uncore.slave.get, 1) }
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// !!! tile.io.slave.foreach { _ <> TileLinkEnqueuer(uncore.slave.get, 1) }
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tile.io.interrupts <> uncore.interrupts
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@ -27,21 +27,19 @@ trait DirectConnection {
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}
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}
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class DefaultCoreplex(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplex(c)(p) {
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override lazy val module = Module(new DefaultCoreplexModule(c, this, new DefaultCoreplexBundle(c)(p))(p))
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class DefaultCoreplex(implicit p: Parameters) extends BaseCoreplex {
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override lazy val module = new DefaultCoreplexModule(this, new DefaultCoreplexBundle(this))
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}
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class DefaultCoreplexBundle(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplexBundle(c)(p)
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class DefaultCoreplexBundle[+L <: DefaultCoreplex](outer: L) extends BaseCoreplexBundle(outer)
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class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle](
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c: CoreplexConfig, l: L, b: B)(implicit p: Parameters) extends BaseCoreplexModule(c, l, b)(p)
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class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle[L]](outer: L, io: B) extends BaseCoreplexModule(outer, io)
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with DirectConnection
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/////
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trait TileClockResetBundle {
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val c: CoreplexConfig
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val tcrs = Vec(c.nTiles, new Bundle {
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trait TileClockResetBundle extends HasCoreplexParameters {
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val tcrs = Vec(nTiles, new Bundle {
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val clock = Clock(INPUT)
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val reset = Bool(INPUT)
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})
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@ -58,7 +56,7 @@ trait AsyncConnection {
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(uncore.cached zip tile.io.cached) foreach { case (u, t) => u <> AsyncTileLinkFrom(tcr.clock, tcr.reset, t) }
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(uncore.uncached zip tile.io.uncached) foreach { case (u, t) => u <> AsyncUTileLinkFrom(tcr.clock, tcr.reset, t) }
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tile.io.slave.foreach { _ <> AsyncUTileLinkTo(tcr.clock, tcr.reset, uncore.slave.get)}
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// !!! tile.io.slave.foreach { _ <> AsyncUTileLinkTo(tcr.clock, tcr.reset, uncore.slave.get)}
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val ti = tile.io.interrupts
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val ui = uncore.interrupts
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@ -73,13 +71,12 @@ trait AsyncConnection {
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}
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}
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class MultiClockCoreplex(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplex(c)(p) {
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override lazy val module = Module(new MultiClockCoreplexModule(c, this, new MultiClockCoreplexBundle(c)(p))(p))
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class MultiClockCoreplex(implicit p: Parameters) extends BaseCoreplex {
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override lazy val module = new MultiClockCoreplexModule(this, new MultiClockCoreplexBundle(this))
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}
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class MultiClockCoreplexBundle(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplexBundle(c)(p)
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class MultiClockCoreplexBundle[+L <: MultiClockCoreplex](outer: L) extends BaseCoreplexBundle(outer)
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with TileClockResetBundle
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class MultiClockCoreplexModule[+L <: MultiClockCoreplex, +B <: MultiClockCoreplexBundle](
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c: CoreplexConfig, l: L, b: B)(implicit p: Parameters) extends BaseCoreplexModule(c, l, b)(p)
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class MultiClockCoreplexModule[+L <: MultiClockCoreplex, +B <: MultiClockCoreplexBundle[L]](outer: L, io: B) extends BaseCoreplexModule(outer, io)
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with AsyncConnection
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