From 81d631a6a1d9323f876b87e8af7f23042c33e3f0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Klemens=20Sch=C3=B6lhorn?= <klemens@schoelhorn.eu>
Date: Sat, 19 May 2018 18:56:56 +0200
Subject: [PATCH] Add small rocket config with fpu and mmu

This is required for booting linux. The caches are still as small as
in the small core config, so performance will not be great.
---
 src/main/scala/subsystem/Configs.scala | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/src/main/scala/subsystem/Configs.scala b/src/main/scala/subsystem/Configs.scala
index 98f3a3f8..34020c03 100644
--- a/src/main/scala/subsystem/Configs.scala
+++ b/src/main/scala/subsystem/Configs.scala
@@ -50,6 +50,28 @@ class WithNBigCores(n: Int) extends Config((site, here, up) => {
   }
 })
 
+class WithNSmallLinuxCores(n: Int) extends Config((site, here, up) => {
+  case RocketTilesKey => {
+    val small = RocketTileParams(
+      core = RocketCoreParams(),
+      btb = None,
+      dcache = Some(DCacheParams(
+        rowBits = site(SystemBusKey).beatBits,
+        nSets = 64,
+        nWays = 1,
+        nTLBEntries = 4,
+        nMSHRs = 0,
+        blockBytes = site(CacheBlockBytes))),
+      icache = Some(ICacheParams(
+        rowBits = site(SystemBusKey).beatBits,
+        nSets = 64,
+        nWays = 1,
+        nTLBEntries = 4,
+        blockBytes = site(CacheBlockBytes))))
+    List.tabulate(n)(i => small.copy(hartId = i))
+  }
+})
+
 class WithNSmallCores(n: Int) extends Config((site, here, up) => {
   case RocketTilesKey => {
     val small = RocketTileParams(