diff --git a/.gitignore b/.gitignore index 353d553c..ffd79035 100644 --- a/.gitignore +++ b/.gitignore @@ -1,2 +1,3 @@ target/ project/target +*.swp diff --git a/Makefrag b/Makefrag index 0ef0653c..497b04b2 100644 --- a/Makefrag +++ b/Makefrag @@ -109,6 +109,7 @@ asm_p_tests = \ rv64uf-p-fcmp \ rv64uf-p-fcvt \ rv64uf-p-fcvt_w \ + rv64uf-p-fclass \ rv64uf-p-fadd \ rv64uf-p-fmin \ rv64uf-p-fmadd \ @@ -205,6 +206,7 @@ asm_v_tests = \ rv64uf-v-fcmp \ rv64uf-v-fcvt \ rv64uf-v-fcvt_w \ + rv64uf-v-fclass \ rv64uf-v-fadd \ rv64uf-v-fmin \ rv64uf-v-fmadd \ diff --git a/chisel b/chisel index 25a33ba1..dff97c5b 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit 25a33ba1d456294fe4ebc79fe95339a0d9d20e8a +Subproject commit dff97c5b52e052637582eaaf7e819b7bf9d1953d diff --git a/csrc/emulator.cc b/csrc/emulator.cc index 6b90d469..f7d73aaa 100644 --- a/csrc/emulator.cc +++ b/csrc/emulator.cc @@ -139,7 +139,7 @@ int main(int argc, char** argv) if (htif->exit_code()) { - fprintf(stderr, "*** FAILED *** (code = %d) after %lld cycles\n", htif->exit_code(), (long long)trace_count); + fprintf(stderr, "*** FAILED *** (code = %d, seed %d) after %lld cycles\n", htif->exit_code(), random_seed, (long long)trace_count); ret = htif->exit_code(); } else if (trace_count == max_cycles) diff --git a/csrc/vcs_main.cc b/csrc/vcs_main.cc index a406a826..cc9e4a06 100644 --- a/csrc/vcs_main.cc +++ b/csrc/vcs_main.cc @@ -8,12 +8,41 @@ #include #include -static htif_emulator_t* htif = NULL; -static unsigned htif_bytes; -static mm_t* mm = NULL; - extern "C" { +extern int vcs_main(int argc, char** argv); + +static htif_emulator_t* htif; +static unsigned htif_bytes; +static mm_t* mm; +static const char* loadmem; + +void htif_fini(vc_handle failure) +{ + delete htif; + htif = NULL; + exit(vc_getScalar(failure)); +} + +int main(int argc, char** argv) +{ + bool dramsim = false; + + for (int i = 1; i < argc; i++) + { + if (!strcmp(argv[i], "+dramsim")) + dramsim = true; + else if (!strncmp(argv[i], "+loadmem=", 9)) + loadmem = argv[i]+9; + } + + mm = dramsim ? (mm_t*)(new mm_dramsim2_t) : (mm_t*)(new mm_magic_t); + htif = new htif_emulator_t(std::vector(argv + 1, argv + argc)); + + vcs_main(argc, argv); + abort(); // should never get here +} + void memory_tick( vc_handle mem_req_val, vc_handle mem_req_rdy, @@ -62,55 +91,18 @@ void memory_tick( ); } -void htif_init -( - vc_handle htif_width, - vc_handle mem_width, - vc_handle argv, - vc_handle loadmem, - vc_handle dramsim -) +void htif_init(vc_handle htif_width, vc_handle mem_width) { int mw = vc_4stVectorRef(mem_width)->d; - mm = vc_getScalar(dramsim) ? (mm_t*)(new mm_dramsim2_t) : (mm_t*)(new mm_magic_t); assert(mw && (mw & (mw-1)) == 0); mm->init(MEM_SIZE, mw/8, LINE_SIZE); + if (loadmem) + load_mem(mm->get_data(), loadmem); + vec32* w = vc_4stVectorRef(htif_width); assert(w->d <= 32 && w->d % 8 == 0); // htif_tick assumes data fits in a vec32 htif_bytes = w->d/8; - - char loadmem_str[1024]; - vc_VectorToString(loadmem, loadmem_str); - if (*loadmem_str) - load_mem(mm->get_data(), loadmem_str); - - char argv_str[1024]; - vc_VectorToString(argv, argv_str); - if (!*argv_str) - { - if (*loadmem_str) - strcpy(argv_str, "none"); - else - { - fprintf(stderr, "Usage: ./simv [host options] +argv=\" [target args]\"\n"); - exit(-1); - } - } - - std::vector args; - std::stringstream ss(argv_str); - std::istream_iterator begin(ss), end; - std::copy(begin, end, std::back_inserter>(args)); - - htif = new htif_emulator_t(args); -} - -void htif_fini(vc_handle failure) -{ - delete htif; - htif = NULL; - exit(vc_getScalar(failure)); } void htif_tick diff --git a/hardfloat b/hardfloat index 39a08130..4a938b1a 160000 --- a/hardfloat +++ b/hardfloat @@ -1 +1 @@ -Subproject commit 39a08130d41ceb9e7f98fa7092fc38970009a460 +Subproject commit 4a938b1aae6df5609400235448583c5c34b47da4 diff --git a/project/build.scala b/project/build.scala index a6f98650..877c66a4 100644 --- a/project/build.scala +++ b/project/build.scala @@ -31,7 +31,8 @@ object BuildSettings extends Build { lazy val uncore = Project("uncore", file("uncore"), settings = buildSettings) dependsOn(hardfloat) lazy val rocket = Project("rocket", file("rocket"), settings = buildSettings) dependsOn(uncore) lazy val hwacha = Project("hwacha", file("hwacha"), settings = buildSettings) dependsOn(uncore, rocket) - lazy val referencechip = Project("referencechip", file("."), settings = buildSettings ++ chipSettings) dependsOn(rocket, hwacha) + lazy val rekall = Project("rekall", file("rekall"), settings = buildSettings) dependsOn(chisel) + lazy val referencechip = Project("referencechip", file("."), settings = buildSettings ++ chipSettings) dependsOn(rocket, hwacha, rekall) val elaborateTask = InputKey[Unit]("elaborate", "convert chisel components into backend source code") val makeTask = InputKey[Unit]("make", "trigger backend-specific makefile command") diff --git a/riscv-tests b/riscv-tests index ea6edc71..629d7edf 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit ea6edc71edb84d9eb9241decd04ee3374a895f0c +Subproject commit 629d7edf826573a9bf297486999e23a7b745c44d diff --git a/riscv-tools b/riscv-tools index ebb909ab..bc6bbf50 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit ebb909ab9dfff8387449faa5827d47eda693b70b +Subproject commit bc6bbf5024bc5297a928b8620ad0364e44d26cfe diff --git a/rocket b/rocket index 49f633cd..ea4b1dfd 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 49f633cd12de6e69479943d8089563edae7e03f5 +Subproject commit ea4b1dfd17ac7e873f59f8c878dd0a214cf4f868 diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 9355a8ed..2279345f 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -7,6 +7,7 @@ import rocket.Util._ import ReferenceChipBackend._ import scala.collection.mutable.ArrayBuffer import scala.collection.mutable.HashMap +import DRAMModel._ object DummyTopLevelConstants { val NTILES = 1 @@ -39,7 +40,7 @@ class ReferenceChipBackend extends VerilogBackend } def addMemPin(c: Module) = { - for (node <- Module.nodes) { + for (mod <- Module.components; node <- mod.nodes) { if (node.isInstanceOf[Mem[ _ ]] && node.component != null && node.asInstanceOf[Mem[_]].seqRead) { connectMemPin(c, node.component, node) } @@ -83,6 +84,8 @@ class ReferenceChipBackend extends VerilogBackend transforms += ((c: Module) => collectNodesIntoComp(initializeDFS)) } +class Fame1ReferenceChipBackend extends ReferenceChipBackend with Fame1Transform + class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module { implicit val (tl, ln, l2) = (conf.tl, conf.tl.ln, conf.l2) @@ -237,8 +240,9 @@ class MemDessert extends Module { io.wide <> x.io.wide } + class Top extends Module { - val co = if(ENABLE_SHARING) { + val co = if(ENABLE_SHARING) { if(ENABLE_CLEAN_EXCLUSIVE) new MESICoherence else new MSICoherence } else { @@ -251,8 +255,8 @@ class Top extends Module { implicit val l2 = L2CoherenceAgentConfiguration(tl, NL2_REL_XACTS, NL2_ACQ_XACTS) implicit val uc = UncoreConfiguration(l2, tl, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64) - val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 38) - val dc = DCacheConfig(128, 4, ntlb = 8, + val ic = ICacheConfig(128, 2, ntlb = 8, btb = BTBConfig(64, 2)) + val dc = DCacheConfig(128, 4, ntlb = 8, nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates) val vic = ICacheConfig(128, 1) val hc = hwacha.HwachaConfiguration(vic, dc, 8, 256, ndtlb = 8, nptlb = 2) @@ -295,3 +299,5 @@ class Top extends Module { io.mem_backup_en <> uncore.io.mem_backup_en io.mem <> uncore.io.mem } + + diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala index f454fe0a..cce6370e 100644 --- a/src/main/scala/fpga.scala +++ b/src/main/scala/fpga.scala @@ -4,6 +4,7 @@ import Chisel._ import Node._ import uncore._ import rocket._ +import DRAMModel._ class FPGAOuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module { @@ -77,10 +78,19 @@ class FPGAUncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Mo htif.io.host.in <> io.host.in } -class FPGATopIO(htifWidth: Int) extends TopIO(htifWidth) +class ReferenceChip(htif_width: Int) extends Module { + val io = new Bundle { + val host_in = new DecoupledIO(new HostPacket(htif_width)).flip() + val host_out = new DecoupledIO(new HostPacket(htif_width)) + val host_clk = Bool(OUTPUT) + val host_clk_edge = Bool(OUTPUT) + val host_debug_stats_pcr = Bool(OUTPUT) -class FPGATop extends Module { - val htif_width = 16 + val mem_req_cmd = new DecoupledIO(new MemReqCmd()) + val mem_req_data = new DecoupledIO(new MemData()) + val mem_resp = (new DecoupledIO(new MemResp())).flip() + } + val co = new MESICoherence val ntiles = 1 val nbanks = 1 @@ -90,13 +100,11 @@ class FPGATop extends Module { implicit val l2 = L2CoherenceAgentConfiguration(tl, 1, 8) implicit val uc = UncoreConfiguration(l2, tl, ntiles, nbanks, bankIdLsb = 5, nSCR = 64) - val ic = ICacheConfig(64, 1, ntlb = 4, nbtb = 4) + val ic = ICacheConfig(64, 1, ntlb = 4, btb = BTBConfig(4)) val dc = DCacheConfig(64, 1, ntlb = 4, nmshr = 2, nrpq = 16, nsdq = 17, states = co.nClientStates) val rc = RocketConfiguration(tl, ic, dc, fpu = None, fastMulDiv = false) - val io = new FPGATopIO(htif_width) - val resetSigs = Vec.fill(uc.nTiles){Bool()} val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc))) val uncore = Module(new FPGAUncore(htif_width)) @@ -118,9 +126,88 @@ class FPGATop extends Module { hl.ipi_req <> Queue(tile.io.host.ipi_req) tile.io.host.ipi_rep <> Queue(hl.ipi_rep) } + + io.host_in.ready := uncore.io.host.in.ready + uncore.io.host.in.bits := io.host_in.bits.data + uncore.io.host.in.valid := io.host_in.valid + + uncore.io.host.out.ready := io.host_out.ready + io.host_out.bits.data := uncore.io.host.out.bits + io.host_out.valid := uncore.io.host.out.valid + + io.host_clk := uncore.io.host.clk + io.host_clk_edge := uncore.io.host.clk_edge + io.host_debug_stats_pcr := uncore.io.host.debug_stats_pcr - io.host <> uncore.io.host - io.mem <> uncore.io.mem + io.mem_req_cmd <> uncore.io.mem.req_cmd + io.mem_req_data <> uncore.io.mem.req_data + io.mem_resp <> uncore.io.mem.resp +} + + +class FPGATopIO(htifWidth: Int) extends TopIO(htifWidth) + +class FPGATop extends Module { + val htif_width = 16 + val io = new FPGATopIO(htif_width) + + val referenceChip = Module(new Fame1Wrapper(new ReferenceChip(htif_width))) + val dramModel = Module(new DRAMSystemWrapper()) + //dram model parameters setup + dramModel.io.params.tRAS := UInt(4) + dramModel.io.params.tRCD := UInt(4) + dramModel.io.params.tRP := UInt(4) + dramModel.io.params.tCCD := UInt(4) + dramModel.io.params.tRTP := UInt(4) + dramModel.io.params.tWTR := UInt(4) + dramModel.io.params.tWR := UInt(4) + dramModel.io.params.tRRD := UInt(4) + + //host to reference chip connections + referenceChip.DecoupledIOs("host_in").host_valid := Bool(true) + referenceChip.DecoupledIOs("host_in").target.bits := io.host.in.bits + referenceChip.DecoupledIOs("host_in").target.valid := io.host.in.valid + io.host.in.ready := referenceChip.DecoupledIOs("host_in").host_ready && referenceChip.DecoupledIOs("host_in").target.ready + + io.host.out.valid := referenceChip.DecoupledIOs("host_out").host_valid && referenceChip.DecoupledIOs("host_out").target.valid + io.host.out.bits := referenceChip.DecoupledIOs("host_out").target.bits + referenceChip.DecoupledIOs("host_out").target.ready := io.host.out.ready + referenceChip.DecoupledIOs("host_out").host_ready := Bool(true) + + io.host.clk := referenceChip.DebugIOs("host_clk") + io.host.clk_edge := referenceChip.DebugIOs("host_clk_edge") + io.host.debug_stats_pcr := referenceChip.DebugIOs("host_debug_stats_pcr") + + //reference chip to dram model connections + val mem_req_cmd_queue = Module(new FameQueue(8)(new MemReqCmd())) + val mem_req_data_queue = Module(new FameQueue(8)(new MemData())) + val mem_resp_queue = Module(new FameQueue(8)(new MemResp())) + + //cmd queue + FameDecoupledIO.connect(referenceChip.DecoupledIOs("mem_req_cmd"), mem_req_cmd_queue.io.enq, new MemReqCmd) + mem_req_cmd_queue.io.deq <> dramModel.io.memReqCmd + + //data queue + FameDecoupledIO.connect(referenceChip.DecoupledIOs("mem_req_data"), mem_req_data_queue.io.enq, new MemData) + mem_req_data_queue.io.deq <> dramModel.io.memReqData + + //resp queue + mem_resp_queue.io.enq <> dramModel.io.memResp + FameDecoupledIO.connect(referenceChip.DecoupledIOs("mem_resp"), mem_resp_queue.io.deq, new MemResp) + + //dram model to outside memory connections + val host_mem_cmd_queue = Module(new Queue(new MemReqCmd, 2)) + val host_mem_data_queue = Module(new Queue(new MemData, REFILL_CYCLES)) + val host_mem_resp_queue = Module(new Queue(new MemResp, REFILL_CYCLES)) + + host_mem_cmd_queue.io.enq <> dramModel.io.mem.req_cmd + host_mem_cmd_queue.io.deq <> io.mem.req_cmd + + host_mem_data_queue.io.enq <> dramModel.io.mem.req_data + host_mem_data_queue.io.deq <> io.mem.req_data + + host_mem_resp_queue.io.enq <> io.mem.resp + host_mem_resp_queue.io.deq <> dramModel.io.mem.resp } abstract class AXISlave extends Module {