riscv/rocket-chip
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Make it easier to override the 'placeholder' Real-Time-Clock, to allow more real-world applications

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Megan Wachs committed 2016-09-02 11:11:40 -07:00
1 parent 4a7972be31
commit 8163a6b597
4 files changed
+15 -4
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src/main/scala/coreplex/Configs.scala
-1
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@@ -128,7 +128,6 @@ class BaseCoreplexConfig extends Config (
case MtvecInit => BigInt(0x1010)
case MtvecWritable => true
//Uncore Paramters
case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients
case LNHeaderBits => log2Ceil(site(TLKey(site(TLId))).nManagers) +
log2Up(site(TLKey(site(TLId))).nClients)