[tilelink2] Make map generation in RRTests a def so that multiple RRTests can be instantiated as part of the same unit test suite. (#356)
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@ -182,7 +182,7 @@ object RRTest0Map
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def ee(bits: Int) = combo(bits, delay(11), delay(11))
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def ee(bits: Int) = combo(bits, delay(11), delay(11))
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// All fields must respect byte alignment, or else it won't behave like an SRAM
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// All fields must respect byte alignment, or else it won't behave like an SRAM
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val map = Seq(
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def map = Seq(
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0 -> Seq(aa(8), ar(8), ad(8), ae(8)),
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0 -> Seq(aa(8), ar(8), ad(8), ae(8)),
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4 -> Seq(ra(8), rr(8), rd(8), re(8)),
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4 -> Seq(ra(8), rr(8), rd(8), re(8)),
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8 -> Seq(da(8), dr(8), dd(8), de(8)),
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8 -> Seq(da(8), dr(8), dd(8), de(8)),
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@ -202,7 +202,7 @@ object RRTest1Map
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def bp(bits: Int) = request(bits, busy, pipe(3))
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def bp(bits: Int) = request(bits, busy, pipe(3))
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def bb(bits: Int) = request(bits, busy, busy)
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def bb(bits: Int) = request(bits, busy, busy)
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val map = RRTest0Map.map.take(6) ++ Seq(
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def map = RRTest0Map.map.take(6) ++ Seq(
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24 -> Seq(pp(8), pb(8), bp(8), bb(8)),
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24 -> Seq(pp(8), pb(8), bp(8), bb(8)),
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28 -> Seq(pp(3), pb(5), bp(1), bb(7), pb(5), bp(3), pp(4), bb(4)))
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28 -> Seq(pp(3), pb(5), bp(1), bb(7), pb(5), bp(3), pp(4), bb(4)))
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}
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}
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