riscv/rocket-chip
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Don't use Vec as lvalue

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Andrew Waterman 2017-03-29 22:04:51 -07:00
parent d3bc99e253
commit 80fb002962
1 changed files with 1 additions and 1 deletions
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src/main/scala/tile/Interrupts.scala
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@ -45,7 +45,7 @@ trait HasExternalInterruptsModule {
// go from flat diplomatic Interrupts to bundled TileInterrupts
def decodeCoreInterrupts(core: TileInterrupts) {
val core_ips = Vec(
val core_ips = Seq(
core.debug,
core.msip,
core.mtip,