Make DTIM deduplicatable

src/main/scala/rocket/DCache.scala

@@ -138,7 +138,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
     if (usingDataScratchpad) {
       metaWriteArb.io.out.ready := true
       metaReadArb.io.out.ready := !metaWriteArb.io.out.valid
-      val inScratchpad = outer.scratch().map(_.contains(s1_paddr)).getOrElse(Bool(false))
+      val baseAddr = GetPropertyByHartId(p(coreplex.RocketTilesKey), _.dcache.flatMap(_.scratch.map(_.U)), io.hartid)
+      val inScratchpad = s1_paddr >= baseAddr && s1_paddr < baseAddr + nSets * cacheBlockBytes
       val hitState = Mux(inScratchpad, ClientMetadata.maximum, ClientMetadata.onReset)
       (inScratchpad, hitState, L1Metadata(UInt(0), ClientMetadata.onReset))
     } else {

src/main/scala/rocket/HellaCache.scala

@@ -160,6 +160,7 @@ abstract class HellaCache(implicit p: Parameters) extends LazyModule {
 
 class HellaCacheBundle(outer: HellaCache) extends Bundle {
   implicit val p = outer.p
+  val hartid = UInt(INPUT, p(XLen))
   val cpu = (new HellaCacheIO).flip
   val ptw = new TLBPTWIO()
   val mem = outer.node.bundleOut

src/main/scala/rocket/Tile.scala

@@ -133,6 +133,7 @@ class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => ne
   outer.frontend.module.io.cpu <> core.io.imem
   outer.frontend.module.io.resetVector := io.resetVector
   outer.frontend.module.io.hartid := io.hartid
+  outer.dcache.module.io.hartid := io.hartid
   dcachePorts += core.io.dmem // TODO outer.dcachePorts += () => module.core.io.dmem ??
   fpuOpt foreach { fpu => core.io.fpu <> fpu.io }
   core.io.ptw <> ptw.io.dpath