riscv/rocket-chip
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Make DTIM deduplicatable

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This commit is contained in:
Andrew Waterman 2017-04-26 15:54:43 -07:00
parent 418879a47f
commit 80d826b94a
3 changed files with 4 additions and 1 deletions
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3
src/main/scala/rocket/DCache.scala
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@ -138,7 +138,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
if (usingDataScratchpad) { if (usingDataScratchpad) {
metaWriteArb.io.out.ready := true metaWriteArb.io.out.ready := true
metaReadArb.io.out.ready := !metaWriteArb.io.out.valid metaReadArb.io.out.ready := !metaWriteArb.io.out.valid
val inScratchpad = outer.scratch().map(_.contains(s1_paddr)).getOrElse(Bool(false)) val baseAddr = GetPropertyByHartId(p(coreplex.RocketTilesKey), _.dcache.flatMap(_.scratch.map(_.U)), io.hartid)
val inScratchpad = s1_paddr >= baseAddr && s1_paddr < baseAddr + nSets * cacheBlockBytes
val hitState = Mux(inScratchpad, ClientMetadata.maximum, ClientMetadata.onReset) val hitState = Mux(inScratchpad, ClientMetadata.maximum, ClientMetadata.onReset)
(inScratchpad, hitState, L1Metadata(UInt(0), ClientMetadata.onReset)) (inScratchpad, hitState, L1Metadata(UInt(0), ClientMetadata.onReset))
} else { } else {

1
src/main/scala/rocket/HellaCache.scala
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@ -160,6 +160,7 @@ abstract class HellaCache(implicit p: Parameters) extends LazyModule {
class HellaCacheBundle(outer: HellaCache) extends Bundle { class HellaCacheBundle(outer: HellaCache) extends Bundle {
implicit val p = outer.p implicit val p = outer.p
val hartid = UInt(INPUT, p(XLen))
val cpu = (new HellaCacheIO).flip val cpu = (new HellaCacheIO).flip
val ptw = new TLBPTWIO() val ptw = new TLBPTWIO()
val mem = outer.node.bundleOut val mem = outer.node.bundleOut

1
src/main/scala/rocket/Tile.scala
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@ -133,6 +133,7 @@ class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => ne
outer.frontend.module.io.cpu <> core.io.imem outer.frontend.module.io.cpu <> core.io.imem
outer.frontend.module.io.resetVector := io.resetVector outer.frontend.module.io.resetVector := io.resetVector
outer.frontend.module.io.hartid := io.hartid outer.frontend.module.io.hartid := io.hartid
outer.dcache.module.io.hartid := io.hartid
dcachePorts += core.io.dmem // TODO outer.dcachePorts += () => module.core.io.dmem ?? dcachePorts += core.io.dmem // TODO outer.dcachePorts += () => module.core.io.dmem ??
fpuOpt foreach { fpu => core.io.fpu <> fpu.io } fpuOpt foreach { fpu => core.io.fpu <> fpu.io }
core.io.ptw <> ptw.io.dpath core.io.ptw <> ptw.io.dpath