riscv/rocket-chip
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Make DTIM deduplicatable

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This commit is contained in:
Andrew Waterman
2017-04-26 15:54:43 -07:00
parent 418879a47f
commit 80d826b94a
3 changed files with 4 additions and 1 deletions
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3
src/main/scala/rocket/DCache.scala
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@ -138,7 +138,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
if (usingDataScratchpad) {
metaWriteArb.io.out.ready := true
metaReadArb.io.out.ready := !metaWriteArb.io.out.valid
val inScratchpad = outer.scratch().map(_.contains(s1_paddr)).getOrElse(Bool(false))
val baseAddr = GetPropertyByHartId(p(coreplex.RocketTilesKey), _.dcache.flatMap(_.scratch.map(_.U)), io.hartid)
val inScratchpad = s1_paddr >= baseAddr && s1_paddr < baseAddr + nSets * cacheBlockBytes
val hitState = Mux(inScratchpad, ClientMetadata.maximum, ClientMetadata.onReset)
(inScratchpad, hitState, L1Metadata(UInt(0), ClientMetadata.onReset))
} else {