tilelink2 Legacy: it's only an error if it's valid (#264)
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@ -107,7 +107,7 @@ class TLLegacy(implicit val p: Parameters) extends LazyModule with HasTileLinkPa
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out.a.bits.addr_hi := ~(~address | addressMask) >> log2Ceil(tlDataBytes)
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out.a.bits.addr_hi := ~(~address | addressMask) >> log2Ceil(tlDataBytes)
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// TL legacy does not support bus errors
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// TL legacy does not support bus errors
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assert (!out.d.bits.error)
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assert (!out.d.valid || !out.d.bits.error)
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// Recreate the beat address counter
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// Recreate the beat address counter
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val beatCounter = RegInit(UInt(0, width = tlBeatAddrBits))
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val beatCounter = RegInit(UInt(0, width = tlBeatAddrBits))
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