riscv/rocket-chip
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rocket: connect interrupt map for Plic+Clint

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This commit is contained in:
Wesley W. Terpstra
2017-03-01 21:57:00 -08:00
parent 38489ad9b0
commit 7ff9f88ad7
3 changed files with 106 additions and 70 deletions
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42
src/main/scala/coreplex/RocketTiles.scala
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@ -23,14 +23,18 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
private val crossing = p(RocketCrossing)
private val configs = p(RocketTilesKey)
private val rocketTileIntNodes = configs.map { _ => IntInternalOutputNode(IntSinkPortSimple()) }
rocketTileIntNodes.foreach { _ := plic.intnode }
private val rocketTileIntNodes = configs.map { _ => IntInternalOutputNode(IntSinkPortSimple(ports = 2)) }
rocketTileIntNodes.foreach { n =>
n := plic.intnode
n := clint.intnode
}
private def wireInterrupts(x: TileInterrupts, i: Int) {
x := clint.module.io.tiles(i)
x.debug := debug.module.io.debugInterrupts(i)
x.meip := rocketTileIntNodes(i).bundleOut(0)(0)
x.seip.foreach { _ := rocketTileIntNodes(i).bundleOut(0)(1) }
x.seip.foreach { _ := rocketTileIntNodes(i).bundleOut(0)(1) } // optional
x.msip := rocketTileIntNodes(i).bundleOut(1)(0)
x.mtip := rocketTileIntNodes(i).bundleOut(1)(1)
}
val rocketWires: Seq[HasRocketTilesBundle => Unit] = configs.zipWithIndex.map { case (c, i) =>
@ -48,6 +52,16 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
buffer.node :=* tile.masterNode
l1tol2.node :=* buffer.node
tile.slaveNode :*= cbus.node
ResourceBinding {
rocketTileIntNodes(i).edgesIn(0).source.sources.flatMap(_.resources).foreach { r =>
r.bind(tile.device, ResourceInt(11)) // meip
if (c.core.useVM) r.bind(tile.device, ResourceInt(9)) // seip
}
rocketTileIntNodes(i).edgesIn(1).source.sources.flatMap(_.resources).foreach { r =>
r.bind(tile.device, ResourceInt(3)) // msip
r.bind(tile.device, ResourceInt(7)) // mtip
}
}
(io: HasRocketTilesBundle) => {
// leave clock as default (simpler for hierarchical PnR)
tile.module.io.hartid := UInt(i)
@ -63,6 +77,16 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
l1tol2.node :=* sink.node
wrapper.slaveNode :*= source.node
source.node :*= cbus.node
ResourceBinding {
rocketTileIntNodes(i).edgesIn(0).source.sources.flatMap(_.resources).foreach { r =>
r.bind(wrapper.rocket.device, ResourceInt(11)) // meip
if (c.core.useVM) r.bind(wrapper.rocket.device, ResourceInt(9)) // seip
}
rocketTileIntNodes(i).edgesIn(1).source.sources.flatMap(_.resources).foreach { r =>
r.bind(wrapper.rocket.device, ResourceInt(3)) // msip
r.bind(wrapper.rocket.device, ResourceInt(7)) // mtip
}
}
(io: HasRocketTilesBundle) => {
wrapper.module.clock := io.tcrs(i).clock
wrapper.module.reset := io.tcrs(i).reset
@ -79,6 +103,16 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
l1tol2.node :=* sink.node
wrapper.slaveNode :*= source.node
source.node :*= cbus.node
ResourceBinding {
rocketTileIntNodes(i).edgesIn(0).source.sources.flatMap(_.resources).foreach { r =>
r.bind(wrapper.rocket.device, ResourceInt(11)) // meip
if (c.core.useVM) r.bind(wrapper.rocket.device, ResourceInt(9)) // seip
}
rocketTileIntNodes(i).edgesIn(1).source.sources.flatMap(_.resources).foreach { r =>
r.bind(wrapper.rocket.device, ResourceInt(3)) // msip
r.bind(wrapper.rocket.device, ResourceInt(7)) // mtip
}
}
(io: HasRocketTilesBundle) => {
wrapper.module.clock := io.tcrs(i).clock
wrapper.module.reset := io.tcrs(i).reset