riscv/rocket-chip
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add backup memory port (disabled for now)

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This commit is contained in:
Andrew Waterman 2012-03-25 15:49:32 -07:00
parent 1f33f6bb58
commit 7fa93da4f5
2 changed files with 61 additions and 25 deletions
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27
rocket/src/main/scala/htif.scala
View File

@ -58,8 +58,10 @@ class rocketHTIF(w: Int, ncores: Int) extends Component with FourStateCoherence
val rx_count_words = rx_count >> UFix(log2up(short_request_bits/w))
val packet_ram_wen = rx_count(log2up(short_request_bits/w)-1,0).andR &&
io.host.in.valid && io.host.in.ready
val packet_ram = Mem(long_request_bits/short_request_bits-1,
packet_ram_wen, rx_count_words - UFix(1), rx_shifter_in)
val packet_ram = Vec(long_request_bits/short_request_bits-1) { Reg() { Bits(width = short_request_bits) } }
when (packet_ram_wen) {
packet_ram(rx_count_words - UFix(1)) := rx_shifter_in
}
val cmd_readmem :: cmd_writemem :: cmd_readcr :: cmd_writecr :: cmd_ack :: cmd_nack :: Nil = Enum(6) { UFix() }
val cmd = header(3,0)
@ -67,9 +69,9 @@ class rocketHTIF(w: Int, ncores: Int) extends Component with FourStateCoherence
val seqno = header(23,16)
val addr = header(63,24).toUFix
val pcr_addr = addr(19,0)
val pcr_coreid = addr(39,20)
val pcr_wdata = packet_ram(UFix(0))
val pcr_addr = addr(4,0)
val pcr_coreid = if (ncores == 1) UFix(0) else addr(20+log2up(ncores),20)
val pcr_wdata = packet_ram(0)
val nack = Mux(cmd === cmd_readmem || cmd === cmd_writemem, size != UFix((1 << OFFSET_BITS)/8),
Mux(cmd === cmd_readcr || cmd === cmd_writecr, size != UFix(1),
@ -157,9 +159,10 @@ class rocketHTIF(w: Int, ncores: Int) extends Component with FourStateCoherence
var mem_req_data: Bits = null
for (i <- 0 until MEM_DATA_BITS/short_request_bits) {
val idx = Cat(mem_cnt, UFix(i, log2up(MEM_DATA_BITS/short_request_bits)))
packet_ram.write(idx, io.mem.xact_rep.bits.data((i+1)*short_request_bits-1, i*short_request_bits),
state === state_mem_rdata && io.mem.xact_rep.valid)
mem_req_data = Cat(packet_ram.read(idx), mem_req_data)
when (state === state_mem_rdata && io.mem.xact_rep.valid) {
packet_ram(idx) := io.mem.xact_rep.bits.data((i+1)*short_request_bits-1, i*short_request_bits)
}
mem_req_data = Cat(packet_ram(idx), mem_req_data)
}
io.mem.xact_init.valid := state === state_mem_req
io.mem.xact_init.bits.t_type := Mux(cmd === cmd_writemem, X_INIT_WRITE_UNCACHED, X_INIT_READ_UNCACHED)
@ -190,10 +193,10 @@ class rocketHTIF(w: Int, ncores: Int) extends Component with FourStateCoherence
cpu.pcr_req.bits.data := pcr_wdata
cpu.reset := my_reset
when (cpu.pcr_req.valid && cpu.pcr_req.ready && cpu.pcr_req.bits.rw) {
pcr_done := Bool(true)
when (cpu.pcr_req.bits.addr === PCR_RESET) {
my_reset := cpu.pcr_req.bits.data(0)
when (state === state_pcr && me && cmd === cmd_writecr) {
pcr_done := cpu.pcr_req.ready
when (pcr_addr === PCR_RESET) {
my_reset := pcr_wdata(0)
}
}
when (cpu.pcr_rep.valid) {

59
rocket/src/main/scala/top.scala
View File

@ -4,17 +4,21 @@ import Chisel._
import Node._;
import Constants._;
class ioTop(htif_width: Int) extends Bundle {
class ioTop(htif_width: Int, mem_backup_width: Int) extends Bundle {
val debug = new ioDebug();
val host = new ioHost(htif_width);
val host_clk = Bool(OUTPUT)
val mem_backup = new ioMemSerialized(mem_backup_width)
val mem_backup_en = Bool(INPUT)
val mem = new ioMem
}
class Top() extends Component {
class Top() extends Component
{
val clkdiv = 32
val htif_width = 16
val io = new ioTop(htif_width);
val mem_backup_width = 16
val io = new ioTop(htif_width, mem_backup_width);
val tile = new Tile
val htif = new rocketHTIF(htif_width, 1)
@ -23,17 +27,46 @@ class Top() extends Component {
hub.io.tiles(0) <> tile.io.tilelink
hub.io.tiles(1) <> htif.io.mem
io.mem.req_cmd <> Queue(hub.io.mem.req_cmd)
io.mem.req_data <> Queue(hub.io.mem.req_data)
hub.io.mem.resp <> Pipe(io.mem.resp)
// mux between main and backup memory ports
val mem_serdes = new MemSerdes(mem_backup_width)
val mem_cmdq = (new queue(1)) { new MemReqCmd }
mem_cmdq.io.enq <> hub.io.mem.req_cmd
mem_cmdq.io.deq.ready := Mux(io.mem_backup_en, mem_serdes.io.wide.req_cmd.ready, io.mem.req_cmd.ready)
io.mem.req_cmd.valid := mem_cmdq.io.deq.valid && !io.mem_backup_en
io.mem.req_cmd.bits := mem_cmdq.io.deq.bits
mem_serdes.io.wide.req_cmd.valid := mem_cmdq.io.deq.valid && io.mem_backup_en
mem_serdes.io.wide.req_cmd.bits := mem_cmdq.io.deq.bits
val mem_dataq = (new queue(2)) { new MemData }
mem_dataq.io.enq <> hub.io.mem.req_data
mem_dataq.io.deq.ready := Mux(io.mem_backup_en, mem_serdes.io.wide.req_data.ready, io.mem.req_data.ready)
io.mem.req_data.valid := mem_dataq.io.deq.valid && !io.mem_backup_en
io.mem.req_data.bits := mem_dataq.io.deq.bits
mem_serdes.io.wide.req_data.valid := mem_dataq.io.deq.valid && io.mem_backup_en
mem_serdes.io.wide.req_data.bits := mem_dataq.io.deq.bits
// only the main or backup port may respond at any one time
hub.io.mem.resp.valid := io.mem.resp.valid || mem_serdes.io.wide.resp.valid
hub.io.mem.resp.bits := Mux(io.mem.resp.valid, io.mem.resp.bits, mem_serdes.io.wide.resp.bits)
// pad out the HTIF using a divided clock
val slow_io = (new slowIO(64, 16)) { Bits(width = htif_width) }
htif.io.host.out <> slow_io.io.out_fast
io.host.out <> slow_io.io.out_slow
htif.io.host.in <> slow_io.io.in_fast
io.host.in <> slow_io.io.in_slow
io.host_clk := slow_io.io.clk_slow
val hio = (new slowIO(clkdiv, 4)) { Bits(width = htif_width) }
htif.io.host.out <> hio.io.out_fast
io.host.out.valid := hio.io.out_slow.valid
hio.io.out_slow.ready := io.host.out.ready
io.host.out.bits := Mux(reset, io.host.in.bits, hio.io.out_slow.bits)
htif.io.host.in <> hio.io.in_fast
io.host.in <> hio.io.in_slow
io.host_clk := hio.io.clk_slow
// pad out the backup memory link with the HTIF divided clk
val mio = (new slowIO(clkdiv, 4)) { Bits(width = mem_backup_width) }
mem_serdes.io.narrow.req <> mio.io.out_fast
io.mem_backup.req <> mio.io.out_slow
mem_serdes.io.narrow.resp.valid := mio.io.in_fast.valid
mio.io.in_fast.ready := Bool(true)
mem_serdes.io.narrow.resp.bits := mio.io.in_fast.bits
io.mem_backup.resp <> mio.io.in_slow
tile.io.host <> htif.io.cpu(0)
io.debug <> tile.io.host.debug