tilelink2: add hooks for Resources
This commit is contained in:
parent
e322692d16
commit
7f6a250dbf
@ -18,6 +18,7 @@ case class IntRange(start: Int, end: Int)
|
||||
def overlaps(x: IntRange) = start < x.end && x.start < end
|
||||
def offset(x: Int) = IntRange(x+start, x+end)
|
||||
}
|
||||
|
||||
object IntRange
|
||||
{
|
||||
implicit def apply(end: Int): IntRange = apply(0, end)
|
||||
@ -25,6 +26,7 @@ object IntRange
|
||||
|
||||
case class IntSourceParameters(
|
||||
range: IntRange,
|
||||
resources: Seq[Resource] = Seq(),
|
||||
nodePath: Seq[BaseNode] = Seq())
|
||||
{
|
||||
val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
|
||||
@ -74,8 +76,8 @@ object IntImp extends NodeImp[IntSourcePortParameters, IntSinkPortParameters, In
|
||||
}
|
||||
|
||||
case class IntIdentityNode() extends IdentityNode(IntImp)
|
||||
case class IntSourceNode(num: Int) extends SourceNode(IntImp)(
|
||||
if (num == 0) Seq() else Seq(IntSourcePortParameters(Seq(IntSourceParameters(num)))))
|
||||
case class IntSourceNode(num: Int, resources: Seq[Resource] = Nil) extends SourceNode(IntImp)(
|
||||
if (num == 0) Seq() else Seq(IntSourcePortParameters(Seq(IntSourceParameters(num, resources)))))
|
||||
case class IntSinkNode() extends SinkNode(IntImp)(
|
||||
Seq(IntSinkPortParameters(Seq(IntSinkParameters()))))
|
||||
|
||||
@ -90,10 +92,12 @@ case class IntOutputNode() extends OutputNode(IntImp)
|
||||
case class IntInputNode() extends InputNode(IntImp)
|
||||
|
||||
case class IntBlindOutputNode() extends BlindOutputNode(IntImp)(Seq(IntSinkPortParameters(Seq(IntSinkParameters()))))
|
||||
case class IntBlindInputNode(num: Int) extends BlindInputNode(IntImp)(Seq(IntSourcePortParameters(Seq(IntSourceParameters(num)))))
|
||||
case class IntBlindInputNode(num: Int, resources: Seq[Resource] = Nil) extends BlindInputNode(IntImp)(
|
||||
Seq(IntSourcePortParameters(Seq(IntSourceParameters(num, resources)))))
|
||||
|
||||
case class IntInternalOutputNode() extends InternalOutputNode(IntImp)(Seq(IntSinkPortParameters(Seq(IntSinkParameters()))))
|
||||
case class IntInternalInputNode(num: Int) extends InternalInputNode(IntImp)(Seq(IntSourcePortParameters(Seq(IntSourceParameters(num)))))
|
||||
case class IntInternalInputNode(num: Int, resources: Seq[Resource] = Nil) extends InternalInputNode(IntImp)(
|
||||
Seq(IntSourcePortParameters(Seq(IntSourceParameters(num, resources)))))
|
||||
|
||||
class IntXbar()(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
|
@ -9,6 +9,7 @@ import util.RationalDirection
|
||||
|
||||
case class TLManagerParameters(
|
||||
address: Seq[AddressSet],
|
||||
resources: Seq[Resource] = Seq(),
|
||||
regionType: RegionType.T = RegionType.GET_EFFECTS,
|
||||
executable: Boolean = false, // processor can execute from this memory
|
||||
nodePath: Seq[BaseNode] = Seq(),
|
||||
@ -67,6 +68,13 @@ case class TLManagerParameters(
|
||||
// The device had better not support a transfer larger than it's alignment
|
||||
val minAlignment = address.map(_.alignment).min
|
||||
require (minAlignment >= maxTransfer)
|
||||
|
||||
def toResource: ResourceAddress = {
|
||||
ResourceAddress(address,
|
||||
r = supportsAcquireB || supportsGet,
|
||||
w = supportsAcquireT || supportsPutFull,
|
||||
x = executable)
|
||||
}
|
||||
}
|
||||
|
||||
case class TLManagerPortParameters(
|
||||
|
Loading…
Reference in New Issue
Block a user