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async_regs: Make modules have predictable names

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This commit is contained in:
Megan Wachs 2017-08-24 15:33:53 -07:00
parent 0f75ebee92
commit 7f683eeb24
1 changed files with 3 additions and 0 deletions
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src/main/scala/util/AsyncResetReg.scala
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@ -63,6 +63,9 @@ class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module {
} }
io.q := q.asUInt io.q := q.asUInt
override def desiredName = s"AsyncResetRegVec_w${w}_i${init}"
} }
object AsyncResetReg { object AsyncResetReg {