Plusargs -- tilelink timeout detection from the command line (#752)

* util: PlusArg gives Chisel access to the command-line

* tilelink2: add a progress watchdog to Monitors

src/main/scala/uncore/tilelink2/Monitor.scala

@@ -435,6 +435,13 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
     }
 
     inflight := (inflight | a_set) & ~d_clr
+
+    val watchdog = RegInit(UInt(0, width = 32))
+    val limit = util.PlusArg("tilelink_timeout")
+    assert (!inflight.orR || limit === UInt(0) || watchdog < limit, "TileLink timeout expired" + extra)
+
+    watchdog := watchdog + UInt(1)
+    when (bundle.a.fire() || bundle.d.fire()) { watchdog := UInt(0) }
   }
 
   def legalizeDESink(bundle: TLBundleSnoop, edge: TLEdge)(implicit sourceInfo: SourceInfo) {

src/main/scala/util/PlusArg.scala

@@ -0,0 +1,21 @@
+// See LICENSE.SiFive for license details.
+
+package util
+import Chisel._
+
+class plusarg_reader(format: String, default: Int) extends BlackBox(Map(
+    "FORMAT"  -> chisel3.core.StringParam(format),
+    "DEFAULT" -> chisel3.core.IntParam(default))) {
+  val io = new Bundle {
+    val out = UInt(OUTPUT, width = 32)
+  }
+}
+
+object PlusArg
+{
+  // PlusArg("foo") will return 42 if the simulation is run with +foo=42
+  // Do not use this as an initial register value. The value is set in an
+  // initial block and thus accessing it from another initial is racey.
+  def apply(name: String, default: Int = 0): UInt =
+    Module(new plusarg_reader(name + "=%d", default)).io.out
+}