From 7eefc12705f76f96746472b61fc3559e44b946ed Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sun, 7 May 2017 15:14:51 -0700 Subject: [PATCH] Support vectored stvec interrupts, too https://github.com/riscv/riscv-isa-manual/commit/137812654e54e5d765e21909679a2a24a38be123 --- src/main/scala/rocket/CSR.scala | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala index 93089f3b..1df0b1cd 100644 --- a/src/main/scala/rocket/CSR.scala +++ b/src/main/scala/rocket/CSR.scala @@ -478,12 +478,12 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param val trapToDebug = Bool(usingDebug) && (reg_singleStepped || causeIsDebugInt || causeIsDebugTrigger || causeIsDebugBreak || reg_debug) val debugTVec = Mux(reg_debug, Mux(insn_break, UInt(0x800), UInt(0x808)), UInt(0x800)) val delegate = Bool(usingVM) && reg_mstatus.prv <= PRV.S && Mux(cause(xLen-1), reg_mideleg(cause_lsbs), reg_medeleg(cause_lsbs)) + val mtvecBaseAlign = 2 + val mtvecInterruptAlign = log2Ceil(new MIP().getWidth) val notDebugTVec = { val base = Mux(delegate, reg_stvec.sextTo(vaddrBitsExtended), reg_mtvec) - val baseAlign = 2 - val interruptAlign = log2Ceil(new MIP().getWidth) - val interruptOffset = cause(interruptAlign-1, 0) << baseAlign - val interruptVec = Cat(base >> (interruptAlign + baseAlign), interruptOffset) + val interruptOffset = cause(mtvecInterruptAlign-1, 0) << mtvecBaseAlign + val interruptVec = Cat(base >> (mtvecInterruptAlign + mtvecBaseAlign), interruptOffset) Mux(base(0) && cause(cause.getWidth-1), interruptVec, base) } val tvec = Mux(trapToDebug, debugTVec, notDebugTVec) @@ -624,7 +624,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param when (decoded_addr(CSRs.mepc)) { reg_mepc := formEPC(wdata) } when (decoded_addr(CSRs.mscratch)) { reg_mscratch := wdata } if (mtvecWritable) - when (decoded_addr(CSRs.mtvec)) { reg_mtvec := wdata & ~UInt(2, mtvecWidth) } + when (decoded_addr(CSRs.mtvec)) { reg_mtvec := ~(~wdata | 2.U | Mux(wdata(0), UInt(((BigInt(1) << mtvecInterruptAlign) - 1) << mtvecBaseAlign), 0.U)) } when (decoded_addr(CSRs.mcause)) { reg_mcause := wdata & UInt((BigInt(1) << (xLen-1)) + 31) /* only implement 5 LSBs and MSB */ } when (decoded_addr(CSRs.mbadaddr)) { reg_mbadaddr := wdata(vaddrBitsExtended-1,0) } @@ -680,7 +680,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param when (decoded_addr(CSRs.sie)) { reg_mie := (reg_mie & ~reg_mideleg) | (wdata & reg_mideleg) } when (decoded_addr(CSRs.sscratch)) { reg_sscratch := wdata } when (decoded_addr(CSRs.sepc)) { reg_sepc := formEPC(wdata) } - when (decoded_addr(CSRs.stvec)) { reg_stvec := wdata >> 2 << 2 } + when (decoded_addr(CSRs.stvec)) { reg_stvec := ~(~wdata | 2.U | Mux(wdata(0), UInt(((BigInt(1) << mtvecInterruptAlign) - 1) << mtvecBaseAlign), 0.U)) } when (decoded_addr(CSRs.scause)) { reg_scause := wdata & UInt((BigInt(1) << (xLen-1)) + 31) /* only implement 5 LSBs and MSB */ } when (decoded_addr(CSRs.sbadaddr)) { reg_sbadaddr := wdata(vaddrBitsExtended-1,0) } when (decoded_addr(CSRs.mideleg)) { reg_mideleg := wdata & delegable_interrupts }