riscv/rocket-chip
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[rocket] remove rocket-specific require() from HasCoreParameters

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This commit is contained in:
Andrew Waterman 2016-08-02 14:38:33 -07:00
parent 791a27748b
commit 7e9d139e49
1 changed files with 2 additions and 2 deletions
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4
rocket/src/main/scala/rocket.scala
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@ -68,8 +68,7 @@ trait HasCoreParameters extends HasAddrMapParameters {
val nCores = p(NTiles) val nCores = p(NTiles)
// fetchWidth doubled, but coreInstBytes halved, for RVC // fetchWidth doubled, but coreInstBytes halved, for RVC
require(fetchWidth == retireWidth * (4 / coreInstBytes)) val decodeWidth = fetchWidth / (if (usingCompressed) 2 else 1)
require(retireWidth == 1)
// Print out log of committed instructions and their writeback values. // Print out log of committed instructions and their writeback values.
// Requires post-processing due to out-of-order writebacks. // Requires post-processing due to out-of-order writebacks.
@ -208,6 +207,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
ibuf.io.imem <> io.imem.resp ibuf.io.imem <> io.imem.resp
ibuf.io.kill := take_pc ibuf.io.kill := take_pc
require(decodeWidth == 1 /* TODO */ && retireWidth == decodeWidth)
val id_ctrl = Wire(new IntCtrlSigs()).decode(id_inst(0), decode_table) val id_ctrl = Wire(new IntCtrlSigs()).decode(id_inst(0), decode_table)
val id_raddr3 = id_expanded_inst(0).rs3 val id_raddr3 = id_expanded_inst(0).rs3
val id_raddr2 = id_expanded_inst(0).rs2 val id_raddr2 = id_expanded_inst(0).rs2