make sure L2 passes no-alloc acquires through to outer memory
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@ -709,6 +709,7 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
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updatePendingCohWhen(io.inner.release.fire(), pending_coh_on_irel)
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updatePendingCohWhen(io.inner.release.fire(), pending_coh_on_irel)
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mergeDataInner(io.inner.release)
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mergeDataInner(io.inner.release)
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val outerParams = p.alterPartial({ case TLId => p(OuterTLId) })
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// Handle misses or coherence permission upgrades by initiating a new transaction in the outer memory:
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// Handle misses or coherence permission upgrades by initiating a new transaction in the outer memory:
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//
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//
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// If we're allocating in this cache, we can use the current metadata
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// If we're allocating in this cache, we can use the current metadata
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@ -716,11 +717,19 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
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// built-in Acquire from the inner TL to the outer TL
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// built-in Acquire from the inner TL to the outer TL
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io.outer.acquire.valid := state === s_outer_acquire &&
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io.outer.acquire.valid := state === s_outer_acquire &&
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(xact.allocate() || !pending_puts(oacq_data_idx))
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(xact.allocate() || !pending_puts(oacq_data_idx))
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io.outer.acquire.bits := Mux(xact.allocate(), xact_old_meta.coh.outer, ClientMetadata.onReset)
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io.outer.acquire.bits := Mux(xact.allocate(),
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.makeAcquire(
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xact_old_meta.coh.outer.makeAcquire(
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client_xact_id = UInt(0),
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client_xact_id = UInt(0),
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addr_block = xact.addr_block,
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addr_block = xact.addr_block,
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op_code = xact.op_code())
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op_code = xact.op_code()),
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Acquire(
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is_builtin_type = Bool(true),
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a_type = xact.a_type,
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client_xact_id = UInt(0),
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addr_block = xact.addr_block,
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addr_beat = xact.addr_beat,
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union = xact.union)(outerParams))
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io.oacq().data := xact.data_buffer(oacq_data_idx)
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io.oacq().data := xact.data_buffer(oacq_data_idx)
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// Handle the response from outer memory
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// Handle the response from outer memory
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@ -792,7 +801,8 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
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pending_writes := (pending_writes & dropPendingBit(io.data.write)) |
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pending_writes := (pending_writes & dropPendingBit(io.data.write)) |
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addPendingBitWhenBeatHasDataAndAllocs(io.inner.acquire) |
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addPendingBitWhenBeatHasDataAndAllocs(io.inner.acquire) |
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addPendingBitWhenBeatHasData(io.inner.release) |
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addPendingBitWhenBeatHasData(io.inner.release) |
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addPendingBitWhenBeatHasData(io.outer.grant)
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(Fill(refillCycles, xact.allocate()) &
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addPendingBitWhenBeatHasData(io.outer.grant))
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val curr_write_beat = PriorityEncoder(pending_writes)
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val curr_write_beat = PriorityEncoder(pending_writes)
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io.data.write.valid := state === s_busy &&
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io.data.write.valid := state === s_busy &&
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pending_writes.orR &&
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pending_writes.orR &&
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@ -807,7 +817,7 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
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io.data.write.bits.data := xact.data_buffer(curr_write_beat)
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io.data.write.bits.data := xact.data_buffer(curr_write_beat)
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// End a transaction by updating the block metadata
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// End a transaction by updating the block metadata
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io.meta.write.valid := state === s_meta_write
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io.meta.write.valid := (state === s_meta_write) && pending_meta_write
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io.meta.write.bits.id := UInt(trackerId)
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io.meta.write.bits.id := UInt(trackerId)
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io.meta.write.bits.idx := xact.addr_block(idxMSB,idxLSB)
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io.meta.write.bits.idx := xact.addr_block(idxMSB,idxLSB)
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io.meta.write.bits.way_en := xact_way_en
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io.meta.write.bits.way_en := xact_way_en
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@ -864,9 +874,11 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
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(coh.outer.requiresVoluntaryWriteback() ||
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(coh.outer.requiresVoluntaryWriteback() ||
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coh.inner.requiresProbesOnVoluntaryWriteback())
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coh.inner.requiresProbesOnVoluntaryWriteback())
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val needs_inner_probes = tag_match && coh.inner.requiresProbes(xact)
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val needs_inner_probes = tag_match && coh.inner.requiresProbes(xact)
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when(!tag_match || is_hit && pending_coh_on_hit != coh) { pending_meta_write := Bool(true) }
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val should_update_meta = !tag_match && xact.allocate() ||
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is_hit && pending_coh_on_hit != coh
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when (should_update_meta) { pending_meta_write := Bool(true) }
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pending_coh := Mux(is_hit, pending_coh_on_hit, Mux(tag_match, coh, pending_coh_on_miss))
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pending_coh := Mux(is_hit, pending_coh_on_hit, Mux(tag_match, coh, pending_coh_on_miss))
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when(needs_inner_probes) {
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when (needs_inner_probes) {
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val full_sharers = coh.inner.full()
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val full_sharers = coh.inner.full()
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val mask_self = Mux(
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val mask_self = Mux(
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xact.requiresSelfProbe(),
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xact.requiresSelfProbe(),
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