First cut at refactoring unittests into a top-level utility. Individual tests co-located with their DUT. No functional changes.
This commit is contained in:
Henry Cook
Howard Mao
158
src/main/scala/junctions/MultiWidthFifo.scala
Normal file
158
src/main/scala/junctions/MultiWidthFifo.scala
Normal file
@ -0,0 +1,158 @@
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package junctions
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import Chisel._
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import unittest.UnitTest
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class MultiWidthFifo(inW: Int, outW: Int, n: Int) extends Module {
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val io = new Bundle {
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val in = Decoupled(Bits(width = inW)).flip
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val out = Decoupled(Bits(width = outW))
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val count = UInt(OUTPUT, log2Up(n + 1))
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}
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if (inW == outW) {
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val q = Module(new Queue(Bits(width = inW), n))
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q.io.enq <> io.in
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io.out <> q.io.deq
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io.count := q.io.count
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} else if (inW > outW) {
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val nBeats = inW / outW
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require(inW % outW == 0, s"MultiWidthFifo: in: $inW not divisible by out: $outW")
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require(n % nBeats == 0, s"Cannot store $n output words when output beats is $nBeats")
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val wdata = Reg(Vec(n / nBeats, Bits(width = inW)))
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val rdata = Vec(wdata.flatMap { indat =>
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(0 until nBeats).map(i => indat(outW * (i + 1) - 1, outW * i)) })
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val head = Reg(init = UInt(0, log2Up(n / nBeats)))
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val tail = Reg(init = UInt(0, log2Up(n)))
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val size = Reg(init = UInt(0, log2Up(n + 1)))
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when (io.in.fire()) {
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wdata(head) := io.in.bits
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head := head + UInt(1)
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}
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when (io.out.fire()) { tail := tail + UInt(1) }
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size := MuxCase(size, Seq(
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(io.in.fire() && io.out.fire()) -> (size + UInt(nBeats - 1)),
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io.in.fire() -> (size + UInt(nBeats)),
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io.out.fire() -> (size - UInt(1))))
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io.out.valid := size > UInt(0)
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io.out.bits := rdata(tail)
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io.in.ready := size < UInt(n)
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io.count := size
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} else {
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val nBeats = outW / inW
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require(outW % inW == 0, s"MultiWidthFifo: out: $outW not divisible by in: $inW")
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val wdata = Reg(Vec(n * nBeats, Bits(width = inW)))
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val rdata = Vec.tabulate(n) { i =>
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Cat(wdata.slice(i * nBeats, (i + 1) * nBeats).reverse)}
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val head = Reg(init = UInt(0, log2Up(n * nBeats)))
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val tail = Reg(init = UInt(0, log2Up(n)))
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val size = Reg(init = UInt(0, log2Up(n * nBeats + 1)))
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when (io.in.fire()) {
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wdata(head) := io.in.bits
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head := head + UInt(1)
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}
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when (io.out.fire()) { tail := tail + UInt(1) }
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size := MuxCase(size, Seq(
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(io.in.fire() && io.out.fire()) -> (size - UInt(nBeats - 1)),
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io.in.fire() -> (size + UInt(1)),
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io.out.fire() -> (size - UInt(nBeats))))
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io.count := size >> UInt(log2Up(nBeats))
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io.out.valid := io.count > UInt(0)
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io.out.bits := rdata(tail)
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io.in.ready := size < UInt(n * nBeats)
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}
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}
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class MultiWidthFifoTest extends UnitTest {
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val big2little = Module(new MultiWidthFifo(16, 8, 8))
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val little2big = Module(new MultiWidthFifo(8, 16, 4))
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val bl_send = Reg(init = Bool(false))
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val lb_send = Reg(init = Bool(false))
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val bl_recv = Reg(init = Bool(false))
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val lb_recv = Reg(init = Bool(false))
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val bl_finished = Reg(init = Bool(false))
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val lb_finished = Reg(init = Bool(false))
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val bl_data = Vec.tabulate(4){i => UInt((2 * i + 1) * 256 + 2 * i, 16)}
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val lb_data = Vec.tabulate(8){i => UInt(i, 8)}
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val (bl_send_cnt, bl_send_done) = Counter(big2little.io.in.fire(), 4)
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val (lb_send_cnt, lb_send_done) = Counter(little2big.io.in.fire(), 8)
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val (bl_recv_cnt, bl_recv_done) = Counter(big2little.io.out.fire(), 8)
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val (lb_recv_cnt, lb_recv_done) = Counter(little2big.io.out.fire(), 4)
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big2little.io.in.valid := bl_send
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big2little.io.in.bits := bl_data(bl_send_cnt)
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big2little.io.out.ready := bl_recv
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little2big.io.in.valid := lb_send
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little2big.io.in.bits := lb_data(lb_send_cnt)
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little2big.io.out.ready := lb_recv
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val bl_recv_data_idx = bl_recv_cnt >> UInt(1)
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val bl_recv_data = Mux(bl_recv_cnt(0),
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bl_data(bl_recv_data_idx)(15, 8),
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bl_data(bl_recv_data_idx)(7, 0))
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val lb_recv_data = Cat(
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lb_data(Cat(lb_recv_cnt, UInt(1, 1))),
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lb_data(Cat(lb_recv_cnt, UInt(0, 1))))
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when (io.start) {
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bl_send := Bool(true)
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lb_send := Bool(true)
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}
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when (bl_send_done) {
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bl_send := Bool(false)
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bl_recv := Bool(true)
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}
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when (lb_send_done) {
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lb_send := Bool(false)
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lb_recv := Bool(true)
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}
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when (bl_recv_done) {
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bl_recv := Bool(false)
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bl_finished := Bool(true)
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}
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when (lb_recv_done) {
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lb_recv := Bool(false)
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lb_finished := Bool(true)
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}
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io.finished := bl_finished && lb_finished
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val bl_start_recv = Reg(next = bl_send_done)
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val lb_start_recv = Reg(next = lb_send_done)
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assert(!little2big.io.out.valid || little2big.io.out.bits === lb_recv_data,
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"Little to Big data mismatch")
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assert(!big2little.io.out.valid || big2little.io.out.bits === bl_recv_data,
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"Bit to Little data mismatch")
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assert(!lb_start_recv || little2big.io.count === UInt(4),
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"Little to Big count incorrect")
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assert(!bl_start_recv || big2little.io.count === UInt(8),
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"Big to Little count incorrect")
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}
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@ -1,8 +1,6 @@
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package junctions.unittests
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package junctions
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import Chisel._
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import junctions._
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import junctions.NastiConstants._
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import cde.Parameters
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class NastiDemuxDriver(n: Int)(implicit p: Parameters) extends Module {
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@ -93,7 +91,7 @@ class NastiDemuxSlave(implicit p: Parameters) extends NastiModule()(p) {
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io.r.bits := NastiReadDataChannel(id = id, data = value)
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}
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class NastiMemoryDemuxTest(implicit p: Parameters) extends UnitTest {
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class NastiMemoryDemuxTest(implicit p: Parameters) extends unittest.UnitTest {
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val nSlaves = 4
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val driver = Module(new NastiDemuxDriver(nSlaves))
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@ -1,8 +1,6 @@
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package junctions.unittests
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package junctions
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import Chisel._
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import junctions._
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import junctions.NastiConstants._
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import cde.Parameters
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class NastiDriver(dataWidth: Int, burstLen: Int, nBursts: Int)
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@ -76,16 +74,3 @@ class NastiDriver(dataWidth: Int, burstLen: Int, nBursts: Int)
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assert(!io.nasti.r.valid || read_data === expected_data,
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s"NastiDriver got wrong data")
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}
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class HastiTest(implicit p: Parameters) extends UnitTest {
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val sram = Module(new HastiTestSRAM(8))
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val bus = Module(new HastiBus(Seq(a => Bool(true))))
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val conv = Module(new HastiMasterIONastiIOConverter)
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val driver = Module(new NastiDriver(32, 8, 2))
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bus.io.slaves(0) <> sram.io
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bus.io.master <> conv.io.hasti
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conv.io.nasti <> driver.io.nasti
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io.finished := driver.io.finished
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driver.io.start := io.start
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}
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@ -2,6 +2,7 @@ package junctions
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import Chisel._
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import cde.{Parameters, Field}
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import unittest.UnitTest
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object HastiConstants
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{
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@ -547,3 +548,16 @@ class HastiTestSRAM(depth: Int)(implicit p: Parameters) extends HastiModule()(p)
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io.hready := ready
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io.hresp := HRESP_OKAY
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}
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class HastiTest(implicit p: Parameters) extends UnitTest {
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val sram = Module(new HastiTestSRAM(8))
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val bus = Module(new HastiBus(Seq(a => Bool(true))))
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val conv = Module(new HastiMasterIONastiIOConverter)
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val driver = Module(new NastiDriver(32, 8, 2))
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bus.io.slaves(0) <> sram.io
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bus.io.master <> conv.io.hasti
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conv.io.nasti <> driver.io.nasti
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io.finished := driver.io.finished
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driver.io.start := io.start
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}
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@ -1,85 +0,0 @@
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package junctions.unittests
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import Chisel._
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import junctions._
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import junctions.NastiConstants._
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class MultiWidthFifoTest extends UnitTest {
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val big2little = Module(new MultiWidthFifo(16, 8, 8))
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val little2big = Module(new MultiWidthFifo(8, 16, 4))
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val bl_send = Reg(init = Bool(false))
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val lb_send = Reg(init = Bool(false))
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val bl_recv = Reg(init = Bool(false))
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val lb_recv = Reg(init = Bool(false))
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val bl_finished = Reg(init = Bool(false))
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val lb_finished = Reg(init = Bool(false))
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val bl_data = Vec.tabulate(4){i => UInt((2 * i + 1) * 256 + 2 * i, 16)}
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val lb_data = Vec.tabulate(8){i => UInt(i, 8)}
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val (bl_send_cnt, bl_send_done) = Counter(big2little.io.in.fire(), 4)
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val (lb_send_cnt, lb_send_done) = Counter(little2big.io.in.fire(), 8)
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val (bl_recv_cnt, bl_recv_done) = Counter(big2little.io.out.fire(), 8)
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val (lb_recv_cnt, lb_recv_done) = Counter(little2big.io.out.fire(), 4)
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big2little.io.in.valid := bl_send
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big2little.io.in.bits := bl_data(bl_send_cnt)
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big2little.io.out.ready := bl_recv
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little2big.io.in.valid := lb_send
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little2big.io.in.bits := lb_data(lb_send_cnt)
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little2big.io.out.ready := lb_recv
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val bl_recv_data_idx = bl_recv_cnt >> UInt(1)
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val bl_recv_data = Mux(bl_recv_cnt(0),
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bl_data(bl_recv_data_idx)(15, 8),
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bl_data(bl_recv_data_idx)(7, 0))
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val lb_recv_data = Cat(
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lb_data(Cat(lb_recv_cnt, UInt(1, 1))),
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lb_data(Cat(lb_recv_cnt, UInt(0, 1))))
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when (io.start) {
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bl_send := Bool(true)
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lb_send := Bool(true)
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}
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when (bl_send_done) {
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bl_send := Bool(false)
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bl_recv := Bool(true)
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}
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when (lb_send_done) {
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lb_send := Bool(false)
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lb_recv := Bool(true)
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}
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when (bl_recv_done) {
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bl_recv := Bool(false)
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bl_finished := Bool(true)
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}
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when (lb_recv_done) {
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lb_recv := Bool(false)
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lb_finished := Bool(true)
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}
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io.finished := bl_finished && lb_finished
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val bl_start_recv = Reg(next = bl_send_done)
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val lb_start_recv = Reg(next = lb_send_done)
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assert(!little2big.io.out.valid || little2big.io.out.bits === lb_recv_data,
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"Little to Big data mismatch")
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assert(!big2little.io.out.valid || big2little.io.out.bits === bl_recv_data,
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"Bit to Little data mismatch")
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assert(!lb_start_recv || little2big.io.count === UInt(4),
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"Little to Big count incorrect")
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assert(!bl_start_recv || big2little.io.count === UInt(8),
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"Big to Little count incorrect")
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}
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@ -1,66 +0,0 @@
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package junctions.unittests
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import Chisel._
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import junctions._
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import cde.{Field, Parameters}
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trait HasUnitTestIO {
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val io = new Bundle {
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val finished = Bool(OUTPUT)
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val start = Bool(INPUT)
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}
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}
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abstract class UnitTest extends Module with HasUnitTestIO {
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when (io.start) {
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printf(s"Started UnitTest ${this.getClass.getSimpleName}\n")
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}
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}
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case object UnitTests extends Field[Parameters => Seq[UnitTest]]
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class UnitTestSuite(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val finished = Bool(OUTPUT)
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}
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val tests = p(UnitTests)(p)
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val s_idle :: s_start :: s_wait :: s_done :: Nil = Enum(Bits(), 4)
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val state = Reg(init = s_idle)
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val test_idx = Reg(init = UInt(0, log2Up(tests.size)))
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val test_finished = Vec(tests.map(_.io.finished))
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when (state === s_idle) { state := s_start }
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when (state === s_start) { state := s_wait }
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when (state === s_wait && test_finished(test_idx)) {
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state := s_start
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test_idx := test_idx + UInt(1)
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state := Mux(test_idx === UInt(tests.size - 1), s_done, s_start)
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}
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val timer = Module(new Timer(500000, tests.size))
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timer.io.start.valid := Bool(false)
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timer.io.stop.valid := Bool(false)
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tests.zipWithIndex.foreach { case (mod, i) =>
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mod.io.start := (state === s_start) && test_idx === UInt(i)
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when (test_idx === UInt(i)) {
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timer.io.start.valid := mod.io.start
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timer.io.start.bits := UInt(i)
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timer.io.stop.valid := mod.io.finished
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timer.io.stop.bits := UInt(i)
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}
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}
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io.finished := (state === s_done)
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assert(!timer.io.timeout.valid, "UnitTest timed out")
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}
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object JunctionsUnitTests {
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def apply(implicit p: Parameters): Seq[UnitTest] =
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Seq(
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Module(new MultiWidthFifoTest),
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Module(new NastiMemoryDemuxTest),
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Module(new HastiTest))
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}
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@ -244,128 +244,3 @@ class DecoupledHelper(val rvs: Seq[Bool]) {
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(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
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}
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}
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class MultiWidthFifo(inW: Int, outW: Int, n: Int) extends Module {
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val io = new Bundle {
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val in = Decoupled(Bits(width = inW)).flip
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val out = Decoupled(Bits(width = outW))
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val count = UInt(OUTPUT, log2Up(n + 1))
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}
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if (inW == outW) {
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val q = Module(new Queue(Bits(width = inW), n))
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q.io.enq <> io.in
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io.out <> q.io.deq
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io.count := q.io.count
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} else if (inW > outW) {
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val nBeats = inW / outW
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require(inW % outW == 0, s"MultiWidthFifo: in: $inW not divisible by out: $outW")
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require(n % nBeats == 0, s"Cannot store $n output words when output beats is $nBeats")
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val wdata = Reg(Vec(n / nBeats, Bits(width = inW)))
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val rdata = Vec(wdata.flatMap { indat =>
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(0 until nBeats).map(i => indat(outW * (i + 1) - 1, outW * i)) })
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val head = Reg(init = UInt(0, log2Up(n / nBeats)))
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val tail = Reg(init = UInt(0, log2Up(n)))
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val size = Reg(init = UInt(0, log2Up(n + 1)))
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when (io.in.fire()) {
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wdata(head) := io.in.bits
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head := head + UInt(1)
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}
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|
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when (io.out.fire()) { tail := tail + UInt(1) }
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|
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size := MuxCase(size, Seq(
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(io.in.fire() && io.out.fire()) -> (size + UInt(nBeats - 1)),
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io.in.fire() -> (size + UInt(nBeats)),
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||||
io.out.fire() -> (size - UInt(1))))
|
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|
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io.out.valid := size > UInt(0)
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io.out.bits := rdata(tail)
|
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io.in.ready := size < UInt(n)
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io.count := size
|
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} else {
|
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val nBeats = outW / inW
|
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|
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require(outW % inW == 0, s"MultiWidthFifo: out: $outW not divisible by in: $inW")
|
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|
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val wdata = Reg(Vec(n * nBeats, Bits(width = inW)))
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val rdata = Vec.tabulate(n) { i =>
|
||||
Cat(wdata.slice(i * nBeats, (i + 1) * nBeats).reverse)}
|
||||
|
||||
val head = Reg(init = UInt(0, log2Up(n * nBeats)))
|
||||
val tail = Reg(init = UInt(0, log2Up(n)))
|
||||
val size = Reg(init = UInt(0, log2Up(n * nBeats + 1)))
|
||||
|
||||
when (io.in.fire()) {
|
||||
wdata(head) := io.in.bits
|
||||
head := head + UInt(1)
|
||||
}
|
||||
|
||||
when (io.out.fire()) { tail := tail + UInt(1) }
|
||||
|
||||
size := MuxCase(size, Seq(
|
||||
(io.in.fire() && io.out.fire()) -> (size - UInt(nBeats - 1)),
|
||||
io.in.fire() -> (size + UInt(1)),
|
||||
io.out.fire() -> (size - UInt(nBeats))))
|
||||
|
||||
io.count := size >> UInt(log2Up(nBeats))
|
||||
io.out.valid := io.count > UInt(0)
|
||||
io.out.bits := rdata(tail)
|
||||
io.in.ready := size < UInt(n * nBeats)
|
||||
}
|
||||
}
|
||||
|
||||
// ============
|
||||
// Static timer
|
||||
// ============
|
||||
|
||||
// Timer with a statically-specified period.
|
||||
// Can take multiple inflight start-stop events with ID
|
||||
// Will continue to count down as long as at least one event is inflight
|
||||
|
||||
class Timer(initCount: Int, maxInflight: Int) extends Module {
|
||||
val io = new Bundle {
|
||||
val start = Valid(UInt(width = log2Up(maxInflight))).flip
|
||||
val stop = Valid(UInt(width = log2Up(maxInflight))).flip
|
||||
val timeout = Valid(UInt(width = log2Up(maxInflight)))
|
||||
}
|
||||
|
||||
val inflight = Reg(init = Vec.fill(maxInflight) { Bool(false) })
|
||||
val countdown = Reg(UInt(width = log2Up(initCount)))
|
||||
val active = inflight.reduce(_ || _)
|
||||
|
||||
when (active) {
|
||||
countdown := countdown - UInt(1)
|
||||
}
|
||||
|
||||
when (io.start.valid) {
|
||||
inflight(io.start.bits) := Bool(true)
|
||||
countdown := UInt(initCount - 1)
|
||||
}
|
||||
when (io.stop.valid) {
|
||||
inflight(io.stop.bits) := Bool(false)
|
||||
}
|
||||
|
||||
io.timeout.valid := countdown === UInt(0) && active
|
||||
io.timeout.bits := PriorityEncoder(inflight)
|
||||
|
||||
assert(!io.stop.valid || inflight(io.stop.bits),
|
||||
"Timer stop for transaction that's not inflight")
|
||||
}
|
||||
|
||||
object Timer {
|
||||
def apply(initCount: Int, start: Bool, stop: Bool): Bool = {
|
||||
val timer = Module(new Timer(initCount, 1))
|
||||
timer.io.start.valid := start
|
||||
timer.io.start.bits := UInt(0)
|
||||
timer.io.stop.valid := stop
|
||||
timer.io.stop.bits := UInt(0)
|
||||
timer.io.timeout.valid
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user