Give TileLink IDs more sensible names

* Outermost -> MCtoEdge
 * MMIO_Outermost -> MMIOtoEdge

Then the corresponding parameters objects are

 * L1toL2 -> innerParams
 * L2toMC -> outerMemParams
 * L2toMMIO -> outerMMIOParams
 * MCtoEdge -> edgeMemParams
 * MMIOtoEdge -> edgeMMIOParams

src/main/scala/coreplex/BaseCoreplex.scala

@@ -31,7 +31,7 @@ trait HasCoreplexParameters {
   lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel)
   lazy val lsb = p(BankIdLSB)
   lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" })
-  lazy val outerParams = p.alterPartial({ case TLId => "L2toMC" })
+  lazy val outerMemParams = p.alterPartial({ case TLId => "L2toMC" })
   lazy val outerMMIOParams = p.alterPartial({ case TLId => "L2toMMIO" })
   lazy val globalAddrMap = p(rocketchip.GlobalAddrMap)
 }
@@ -50,7 +50,7 @@ abstract class BaseCoreplex(c: CoreplexConfig)(implicit p: Parameters) extends L
 
 abstract class BaseCoreplexBundle(val c: CoreplexConfig)(implicit val p: Parameters) extends Bundle with HasCoreplexParameters {
   val master = new Bundle {
-    val mem = Vec(c.nMemChannels, new ClientUncachedTileLinkIO()(outerParams))
+    val mem = Vec(c.nMemChannels, new ClientUncachedTileLinkIO()(outerMemParams))
     val mmio = new ClientUncachedTileLinkIO()(outerMMIOParams)
   }
   val slave = Vec(c.nSlaves, new ClientUncachedTileLinkIO()(innerParams)).flip
@@ -112,7 +112,7 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
     l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner
 
     // Create a converter between TileLinkIO and MemIO for each channel
-    val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, c.nMemChannels)(outerParams))
+    val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, c.nMemChannels)(outerMemParams))
 
     val backendBuffering = TileLinkDepths(0,0,0,0,0)
     for ((bank, icPort) <- managerEndpoints zip mem_ic.io.in) {

src/main/scala/groundtest/NastiTest.scala

@@ -115,7 +115,7 @@ class NastiConverterTest(implicit p: Parameters) extends GroundTest()(p)
 
   val test = Module(new NastiGenerator(genId))
   val converter = Module(new TileLinkIONastiIOConverter()(
-    p.alterPartial { case TLId => "Outermost" }))
+    p.alterPartial { case TLId => "MCtoEdge" }))
 
   converter.io.nasti <> test.io.mem
   TileLinkWidthAdapter(io.mem.head, converter.io.tl)

src/main/scala/rocketchip/Configs.scala

@@ -39,9 +39,9 @@ class BasePlatformConfig extends Config(
             addrBits = Dump("MEM_ADDR_BITS", site(PAddrBits)),
             idBits = Dump("MEM_ID_BITS", site(MIFTagBits)))
         }
-        case TLKey("Outermost") =>
+        case TLKey("MCtoEdge") =>
           site(TLKey("L2toMC")).copy(dataBeats = site(MIFDataBeats))
-        case TLKey("MMIO_Outermost") =>
+        case TLKey("MMIOtoEdge") =>
           site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats))
         case BuildCoreplex =>
           (c: CoreplexConfig, p: Parameters) => uncore.tilelink2.LazyModule(new DefaultCoreplex(c)(p)).module

src/main/scala/rocketchip/Periphery.scala

@@ -82,10 +82,9 @@ trait HasPeripheryParameters {
   lazy val nMemAHBChannels = if (tMemChannels == BusType.AHB) nMemChannels else 0
   lazy val nMemTLChannels  = if (tMemChannels == BusType.TL)  nMemChannels else 0
   lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" })
-  lazy val outerParams = p.alterPartial({ case TLId => "L2toMC" })
   lazy val outerMMIOParams = p.alterPartial({ case TLId => "L2toMMIO" })
-  lazy val outermostParams = p.alterPartial({ case TLId => "Outermost" })
+  lazy val edgeMemParams = p.alterPartial({ case TLId => "MCtoEdge" })
-  lazy val outermostMMIOParams = p.alterPartial({ case TLId => "MMIO_Outermost" })
+  lazy val edgeMMIOParams = p.alterPartial({ case TLId => "MMIOtoEdge" })
   lazy val peripheryBusConfig = p(PeripheryBusKey)
   lazy val cacheBlockBytes = p(CacheBlockBytes)
 }
@@ -163,7 +162,7 @@ trait PeripheryMasterMemBundle extends HasPeripheryParameters {
   val mem_rst = p(AsyncMemChannels).option(Vec(nMemChannels, Bool (INPUT)))
   val mem_axi = Vec(nMemAXIChannels, new NastiIO)
   val mem_ahb = Vec(nMemAHBChannels, new HastiMasterIO)
-  val mem_tl = Vec(nMemTLChannels, new ClientUncachedTileLinkIO()(outermostParams))
+  val mem_tl = Vec(nMemTLChannels, new ClientUncachedTileLinkIO()(edgeMemParams))
 }
 
 trait PeripheryMasterMemModule extends HasPeripheryParameters {
@@ -172,7 +171,7 @@ trait PeripheryMasterMemModule extends HasPeripheryParameters {
   val io: PeripheryMasterMemBundle
   val coreplexIO: BaseCoreplexBundle
 
-  val edgeMem = coreplexIO.master.mem.map(TileLinkWidthAdapter(_, outermostParams))
+  val edgeMem = coreplexIO.master.mem.map(TileLinkWidthAdapter(_, edgeMemParams))
 
   // Abuse the fact that zip takes the shorter of the two lists
   ((io.mem_axi zip edgeMem) zipWithIndex) foreach { case ((axi, mem), idx) =>
@@ -206,7 +205,7 @@ trait PeripheryMasterMMIOBundle extends HasPeripheryParameters {
   val mmio_rst = p(AsyncMMIOChannels).option(Vec(p(NExtMMIOAXIChannels), Bool (INPUT)))
   val mmio_axi = Vec(p(NExtMMIOAXIChannels), new NastiIO)
   val mmio_ahb = Vec(p(NExtMMIOAHBChannels), new HastiMasterIO)
-  val mmio_tl = Vec(p(NExtMMIOTLChannels), new ClientUncachedTileLinkIO()(outermostMMIOParams))
+  val mmio_tl = Vec(p(NExtMMIOTLChannels), new ClientUncachedTileLinkIO()(edgeMMIOParams))
 }
 
 trait PeripheryMasterMMIOModule extends HasPeripheryParameters {
@@ -216,7 +215,7 @@ trait PeripheryMasterMMIOModule extends HasPeripheryParameters {
   val pBus: TileLinkRecursiveInterconnect
 
   val mmio_ports = p(ExtMMIOPorts) map { port =>
-    TileLinkWidthAdapter(pBus.port(port.name), outermostMMIOParams)
+    TileLinkWidthAdapter(pBus.port(port.name), edgeMMIOParams)
   }
 
   val mmio_axi_start = 0