riscv/rocket-chip
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Give TileLink IDs more sensible names

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* Outermost -> MCtoEdge
 * MMIO_Outermost -> MMIOtoEdge

Then the corresponding parameters objects are

 * L1toL2 -> innerParams
 * L2toMC -> outerMemParams
 * L2toMMIO -> outerMMIOParams
 * MCtoEdge -> edgeMemParams
 * MMIOtoEdge -> edgeMMIOParams
This commit is contained in:
Howard Mao
2016-09-27 11:44:11 -07:00
committed by Henry Cook
parent 8a55521b01
commit 7d6fb950b6
4 changed files with 12 additions and 13 deletions
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4
src/main/scala/rocketchip/Configs.scala
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@ -39,9 +39,9 @@ class BasePlatformConfig extends Config(
addrBits = Dump("MEM_ADDR_BITS", site(PAddrBits)),
idBits = Dump("MEM_ID_BITS", site(MIFTagBits)))
}
case TLKey("Outermost") =>
case TLKey("MCtoEdge") =>
site(TLKey("L2toMC")).copy(dataBeats = site(MIFDataBeats))
case TLKey("MMIO_Outermost") =>
case TLKey("MMIOtoEdge") =>
site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats))
case BuildCoreplex =>
(c: CoreplexConfig, p: Parameters) => uncore.tilelink2.LazyModule(new DefaultCoreplex(c)(p)).module